From: sashiko-bot@kernel.org
To: "Wojciech Dubowik" <wojciech.dubowik@mt.com>
Cc: imx@lists.linux.dev, robh@kernel.org, conor+dt@kernel.org,
devicetree@vger.kernel.org, Frank.Li@kernel.org,
dri-devel@lists.freedesktop.org
Subject: Re: [PATCH v3 1/2] drm/bridge: ti-sn65dsi83: Add reversed lvds lanes support
Date: Fri, 10 Jul 2026 08:37:37 +0000 [thread overview]
Message-ID: <20260710083737.BD1CB1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260710082630.394040-3-wojciech.dubowik@mt.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] Probe definitively fails on valid legacy 3-lane or 0-indexed device trees due to rigid array bounds.
--
--- Patch [1]: [PATCH v3 1/2] drm/bridge: ti-sn65dsi83: Add reversed lvds lanes support ---
commit 47fc41c5744e78e6f8072b1226e9548c69361da5
Author: Wojciech Dubowik <Wojciech.Dubowik@mt.com>
drm/bridge: ti-sn65dsi83: Add reversed lvds lanes support
The chip supports output lvds lanes in two orders, default <1 2 3 4>
and <4 3 2 1>. Add parsing of an optional output lvds data-lanes
property so we can inform chip that the lanes have been reversed.
> diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi83.c b/drivers/gpu/drm/bridge/ti-sn65dsi83.c
> --- a/drivers/gpu/drm/bridge/ti-sn65dsi83.c
> +++ b/drivers/gpu/drm/bridge/ti-sn65dsi83.c
[ ... ]
> @@ -854,6 +873,37 @@ static int sn65dsi83_parse_lvds_endpoint(struct sn65dsi83 *ctx, int channel)
> goto exit;
> }
>
> + ret_data = of_property_read_u32_array(endpoint, "data-lanes", data_lanes,
> + ARRAY_SIZE(data_lanes));
> + if (ret_data != 0 && ret_data != -EINVAL) {
[Severity: High]
Does this code break valid legacy device trees that define fewer than 4 lanes?
If a device tree has a data-lanes property on the LVDS endpoint with fewer
than 4 lanes (e.g., <1 2 3>), of_property_read_u32_array() will return
-EOVERFLOW because it rigidly expects exactly ARRAY_SIZE(data_lanes) elements.
This will immediately abort the probe, breaking previously working displays.
> + ret = ret_data;
> + goto exit;
> + }
> +
> + if (!ret_data) {
> + for (i = 0; i < ARRAY_SIZE(supported_data_lane_mapping); i++) {
> + for (j = 0; j < DATA_LANES_COUNT; j++) {
> + if (data_lanes[j] != supported_data_lane_mapping[i][j])
> + break;
> + }
> +
> + if (j == DATA_LANES_COUNT)
> + break;
> + }
> +
> + switch (i) {
> + case NORMAL_LANE_MAPPING:
> + break;
> + case REVERSE_LANE_MAPPING:
> + ctx->lvds_reverse_lanes_conf[channel] = true;
> + break;
> + default:
> + dev_err(dev, "invalid data lanes mapping\n");
> + ret = -EINVAL;
[Severity: High]
Will this cause the probe to fail on 0-indexed device tree configurations?
The array comparison logic above this switch strictly checks for 1-indexed
mappings. If the device tree uses a valid 0-indexed scheme (e.g., <0 1 2 3>),
it falls through to this default case, causing the probe to fail with -EINVAL.
> + goto exit;
> + }
> + }
--
Sashiko AI review · https://sashiko.dev/#/patchset/20260710082630.394040-1-wojciech.dubowik@mt.com?part=1
next prev parent reply other threads:[~2026-07-10 8:37 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20260710082630.394040-1-wojciech.dubowik@mt.com>
[not found] ` <20260710082630.394040-4-wojciech.dubowik@mt.com>
2026-07-10 8:34 ` [PATCH v3 2/2] dt-bindings: display: sn65dsi83: Add output data-lanes sashiko-bot
[not found] ` <20260710082630.394040-3-wojciech.dubowik@mt.com>
2026-07-10 8:37 ` sashiko-bot [this message]
2026-07-10 8:38 ` [PATCH v2] drm/bridge: ti-sn65dsi83: Add reversed lvds lanes support sashiko-bot
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