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From: sashiko-bot@kernel.org
To: "Eliot Courtney" <ecourtney@nvidia.com>
Cc: ojeda@kernel.org, "Alexandre Courbot" <acourbot@nvidia.com>,
	dri-devel@lists.freedesktop.org,
	"Danilo Krummrich" <dakr@kernel.org>
Subject: Re: [PATCH v4 1/5] gpu: nova-core: correct FRTS vidmem offset calculation
Date: Tue, 04 Aug 2026 05:54:40 +0000	[thread overview]
Message-ID: <20260804055441.445401F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260804-blackwell-fixes-v4-1-ac858b6a1935@nvidia.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The r570-specific 2 MiB alignment for the FRTS vidmem offset is incorrectly skipped if the PMU reserved size is zero.
--

--- Patch [1]: [PATCH v4 1/5] gpu: nova-core: correct FRTS vidmem offset calculation ---
commit 8aa662faea789e52a898638a43d6d0e165669003
Author: Eliot Courtney <ecourtney@nvidia.com>

gpu: nova-core: correct FRTS vidmem offset calculation

This commit changes the calculation of the FRTS vidmem offset to use a
per-architecture reserved size plus the PMU reserved size, rather than
relying on coincidental matching with the non-wpr heap size.

> diff --git a/drivers/gpu/nova-core/fsp.rs b/drivers/gpu/nova-core/fsp.rs
> index ba4544210e40f..a81b510282829 100644
> --- a/drivers/gpu/nova-core/fsp.rs
> +++ b/drivers/gpu/nova-core/fsp.rs
> @@ -251,20 +251,31 @@ struct FspCotMessage {
>  }
>  
>  impl FspCotMessage {
> +    /// Computes the FRTS vidmem offset for the Chain-of-Trust message. It is measured backwards
> +    /// from the end of the framebuffer.
> +    fn frts_vidmem_offset(hal: &dyn hal::FspHal, fb_layout: &FbLayout) -> Result<u64> {
> +        let mut offset = u64::from(hal.fb_end_reserved_size());
> +
> +        if fb_layout.pmu_reserved_size != 0 {
> +            offset = (offset + u64::from(fb_layout.pmu_reserved_size))
> +                // The 2 MiB alignment is r570-specific.
> +                .align_up(Alignment::new::<SZ_2M>())
> +                .ok_or(EINVAL)?;
> +        }

[Severity: Medium]
If fb_layout.pmu_reserved_size happens to be 0, this bypasses the 2 MiB
alignment entirely. 

For platforms like GB100 or GB202 where hal.fb_end_reserved_size() is 
SZ_2M + SZ_128K (which is unaligned), wouldn't this result in an unaligned
FRTS offset and potentially cause FSP boot failures? 

Should the 2 MiB alignment step be performed unconditionally even when the 
PMU reservation size is 0?

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260804-blackwell-fixes-v4-0-ac858b6a1935@nvidia.com?part=1

  reply	other threads:[~2026-08-04  5:54 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-04  5:41 [PATCH v4 0/5] gpu: nova-core: blackwell follow-ups and fixes Eliot Courtney
2026-08-04  5:41 ` [PATCH v4 1/5] gpu: nova-core: correct FRTS vidmem offset calculation Eliot Courtney
2026-08-04  5:54   ` sashiko-bot [this message]
2026-08-04 13:08   ` Alexandre Courbot
2026-08-04  5:41 ` [PATCH v4 2/5] gpu: nova-core: rename heap size field Eliot Courtney
2026-08-04  5:41 ` [PATCH v4 3/5] gpu: nova-core: return non-WPR heap size as u64 from HALs Eliot Courtney
2026-08-04  5:51   ` sashiko-bot
2026-08-04  5:41 ` [PATCH v4 4/5] gpu: nova-core: split FbLayout into FSP and non-FSP versions Eliot Courtney
2026-08-04  5:41 ` [PATCH v4 5/5] gpu: nova-core: pass WPR metadata ownership to FmcBootArgs Eliot Courtney
2026-08-05  5:48 ` [PATCH v4 0/5] gpu: nova-core: blackwell follow-ups and fixes Alexandre Courbot

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