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From: sashiko-bot@kernel.org
To: "Alex Huang" <Alex.Huang2@amd.com>
Cc: dri-devel@lists.freedesktop.org
Subject: Re: [PATCH v3 1/4] drm/edid: Parse AMD VSDB for FreeSync refresh range
Date: Tue, 04 Aug 2026 15:17:58 +0000	[thread overview]
Message-ID: <20260804151759.1FAAF1F000E9@smtp.kernel.org> (raw)
In-Reply-To: <20260804143339.714548-2-Alex.Huang2@amd.com>

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] The maximum payload length check in `cea_db_is_amd_vsdb()` rejects payloads larger than 21 bytes, silently breaking the intended forward compatibility for future VSDB versions.
--

--- Patch [1]: [PATCH v3 1/4] drm/edid: Parse AMD VSDB for FreeSync refresh range ---
commit 26fe9de2b3686b271fb4f7932172730167732cdb
Author: Alex Huang <Alex.Huang2@amd.com>

drm/edid: Parse AMD VSDB for FreeSync refresh range

This commit restructures the AMD VSDB parser to support FreeSync refresh
range fields from version 1 and 2 blocks. It also updates the parser to
handle versions > 3 as if they were version 3 for forward compatibility.

> diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> index df3c25bac761d..a12b5e6905fb7 100644
> --- a/drivers/gpu/drm/drm_edid.c
> +++ b/drivers/gpu/drm/drm_edid.c

[ ... ]

> @@ -5231,7 +5259,7 @@ static bool cea_db_is_microsoft_vsdb(const struct cea_db *db)
>  static bool cea_db_is_amd_vsdb(const struct cea_db *db)
>  {
>  	return cea_db_is_vendor(db, AMD_IEEE_OUI) &&
> -		cea_db_payload_len(db) >= AMD_VSDB_V3_PAYLOAD_MIN_LEN &&
> +		cea_db_payload_len(db) >= AMD_VSDB_V1_PAYLOAD_LEN &&
>  		cea_db_payload_len(db) <= AMD_VSDB_V3_PAYLOAD_MAX_LEN;

[Severity: Medium]
Will this hard limit at AMD_VSDB_V3_PAYLOAD_MAX_LEN (21 bytes) prevent the
intended forward compatibility for future VSDB versions?

The commit message notes that versions > 3 will be parsed as if they were
version 3 because future versions will likely be backwards compatible. 
However, if a future version introduces new fields and the payload exceeds
21 bytes, cea_db_is_amd_vsdb() will return false.

Doesn't this mean the block will be completely ignored before it can ever
reach the fallback logic in drm_parse_amd_vsdb()?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260804143339.714548-1-Alex.Huang2@amd.com?part=1

  reply	other threads:[~2026-08-04 15:18 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-04 14:33 [PATCH v3 0/4] drm/edid: Parse AMD VSDB FreeSync range in common code Alex Huang
2026-08-04 14:33 ` [PATCH v3 1/4] drm/edid: Parse AMD VSDB for FreeSync refresh range Alex Huang
2026-08-04 15:17   ` sashiko-bot [this message]
2026-08-04 14:33 ` [PATCH v3 2/4] drm/amd/display: Use HDMI FreeSync range from common EDID parser Alex Huang
2026-08-04 14:33 ` [PATCH v3 3/4] drm/amd/display: Clean up FreeSync capability detection Alex Huang
2026-08-04 15:35   ` sashiko-bot
2026-08-04 14:33 ` [PATCH v3 4/4] drm/amd/display: Remove unused DMCU/DMUB EDID CEA parser Alex Huang
2026-08-04 15:49   ` sashiko-bot

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