Re: [PATCH v2 12/15] phy: rockchip: inno-hdmi: Use the common Innosilicon PHY helpers

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:

Pre-existing issues:
- [High] Kernel panic or division-by-zero exception due to division by zero in clock rate recalculation if hardware registers are uninitialized or zeroed.
- [High] Multiplication of unsigned long values silently overflows on 32-bit architectures before assignment to a 64-bit variable in VCO rate calculation.
--

commit 65afb8fac5b8b08e9749e00354df9fbca4121dd2
Author: Michal Wilczynski <m.wilczynski@samsung.com>

phy: rockchip: inno-hdmi: Use the common Innosilicon PHY helpers

This commit replaces the local RK3328 pre-PLL implementations for calculating
and setting rates with the generic shared Innosilicon helpers. It keeps the
RK3228 register-level code separate due to different register addresses but
shares the table lookup.

> diff --git a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
> index 1483907413faa..fae766607b0ea 100644
> --- a/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
> +++ b/drivers/phy/rockchip/phy-rockchip-inno-hdmi.c
[ ... ]
> @@ -870,39 +850,11 @@ unsigned long inno_hdmi_phy_rk3328_clk_recalc_rate(struct clk_hw *hw,
>  						   unsigned long parent_rate)
>  {
>  	struct inno_hdmi_phy *inno = to_inno_hdmi_phy(hw);
[ ... ]
> +	inno->pixclock = inno_hdmi_phy_pre_pll_recalc_rate(&inno->pre_pll,
> +							   parent_rate);

[Severity: High]
This is a pre-existing issue, but since we are switching to the shared helper
inno_hdmi_phy_pre_pll_recalc_rate(), can this code cause a division by zero?

If the bootloader has not initialized the PHY, the hardware registers may
contain their default 0 values. When the clock framework calls recalc_rate
during registration at boot, would the following logic in the helper result in
a division by zero:

drivers/phy/phy-inno-hdmi.c:inno_hdmi_phy_pre_pll_recalc_rate() {
    ...
	nd = inno_read(pll, INNO_PRE_PLL_DIV_1) & INNO_PRE_PLL_PRE_DIV_MASK;
    ...
	if (inno_read(pll, INNO_PRE_PLL_CONTROL) & INNO_PCLK_VCO_DIV_5_MASK) {
		do_div(vco, nd * 5);
	} else {
		no_a = inno_read(pll, INNO_PCLK_DIV_AB) & INNO_PCLK_DIV_A_MASK;
		no_b = FIELD_GET(INNO_PCLK_DIV_B_MASK,
				 inno_read(pll, INNO_PCLK_DIV_AB)) + 2;
		no_d = inno_read(pll, INNO_PCLK_DIV_CD) & INNO_PCLK_DIV_D_MASK;

		do_div(vco, nd * (no_a == 1 ? no_b : no_a) * no_d * 2);
	}
    ...
}

If nd, no_a, or no_d evaluate to 0, the denominator becomes 0, which could
lead to a kernel panic or exception on some architectures.

[Severity: High]
This isn't a bug introduced by this patch, but does the rate recalculation
silently overflow on 32-bit architectures?

Inside the same helper, the VCO rate is calculated as:

drivers/phy/phy-inno-hdmi.c:inno_hdmi_phy_pre_pll_recalc_rate() {
    ...
	vco = parent_rate * nf;

	if (!(inno_read(pll, INNO_PRE_PLL_DIV_2) &
	      INNO_PRE_PLL_FRAC_DIV_DISABLE)) {
		frac = inno_read(pll, INNO_PRE_PLL_FRAC_DIV_7_0) |
		       (inno_read(pll, INNO_PRE_PLL_FRAC_DIV_15_8) << 8) |
		       (inno_read(pll, INNO_PRE_PLL_FRAC_DIV_23_16) << 16);
		vco += DIV_ROUND_CLOSEST(parent_rate * frac,
					 BIT(INNO_FRAC_DIV_WIDTH));
	}
    ...
}

The parent_rate is typically 24,000,000, while nf can be up to 757 and
frac up to ~14.6 million. Since parent_rate is an unsigned long and nf is a
u16, the multiplication is performed as 32-bit unsigned math on 32-bit
platforms (like RK3228 which uses ARM32).

Would parent_rate * nf and parent_rate * frac wrap around ULONG_MAX before
being assigned to the 64-bit vco variable or before the division in
DIV_ROUND_CLOSEST?

>  
> -	inno->pixclock = DIV_ROUND_CLOSEST((unsigned long)vco, 1000) * 1000;
> -
> -	dev_dbg(inno->dev, "%s rate %lu vco %llu\n",
> -		__func__, inno->pixclock, vco);
> +	dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock);
>  
>  	return inno->pixclock;
>  }

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260828-jh7110-clean-send-v2-0-331680c8b9d1@samsung.com?part=12