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[2001:4c4e:1b83:1700:d60d:5ccf:7970:d839]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49ce4775005sm91395395e9.10.2026.09.02.08.28.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Sep 2026 08:29:01 -0700 (PDT) From: Igor Paunovic To: Cristian Ciocaltea Cc: Igor Paunovic , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Dave Stevenson , Dmitry Baryshkov , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Luca Ceresoli , Chen-Yu Tsai , Samuel Holland , mcanal@igalia.com, Raspberry Pi Kernel Maintenance , Raphael Gallais-Pou , Sandy Huang , Heiko Stuebner , Andy Yan , Algea Cao , Daniel Stone , Liu Ying , Phong LE , Helge Deller , kernel@collabora.com, Dmitry Baryshkov , Diederik de Haas , Maud Spierings , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org Subject: Re: [PATCH v11 00/74] Add HDMI 2.0 support to DW HDMI QP TX Date: Wed, 2 Sep 2026 17:28:35 +0200 Message-ID: <20260902152838.5771-1-royalnet026@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260901-dw-hdmi-qp-scramb-v11-0-bc12954a0688@collabora.com> References: <20260901-dw-hdmi-qp-scramb-v11-0-bc12954a0688@collabora.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi Cristian, > This has been tested on the following boards: One more, with a sink pair your boards cannot cover: Tested-by: Igor Paunovic # RK3588 Orange Pi 5 Plus, dual HDMI Setup: whole v11 on its stated base (drm-misc-next 47b823940e38), both SoC HDMI ports driven at once: a Samsung with HF-VSDB (max TMDS character rate 600 MHz, SCDC present) and a Sony limited to 300 MHz TMDS. 1) HDMI 2.0 path: the Samsung now offers and runs 3840x2160@60 RGB with a 594 MHz pixel clock (modetest-confirmed). Without the series the same port tops out at 4K@30. A stable picture at 594 MHz is only possible with scrambling and the 1/40 TMDS ratio active; it stayed stable across boot, mode changes and hotplug. 2) Non-2.0 fallback: the Sony keeps its 297 MHz 4K@30 modes. No regression. 3) The result I care most about: this Sony in standby keeps EDID/5V up but drops the link, and on my 7.2 stack that generates a storm of detect/modeset cycles - measured 119-194 per hour, enough to make the desktop stutter. On v11, twenty minutes of standby produced ZERO events, and wake restored both sinks by itself. Whatever share of that the cached-status detect and the SCDC-loss handling each take - thank you. 4) Hotplug on both ports: clean detach and reattach, no storms. 5) Audio on a dead link: this morning my 7.2 stack took an SError panic (regmap read in dw_hdmi_qp_bridge_clear_audio_infoframe when a PCM was closed on a link whose SCDC never came up - full UART trace available if useful). On v11 I could not reproduce the class: six open/close cycles against the standby sink plus one natural prepare-failure-then-close during replug all survived cleanly. Caveat: different base kernels, so this is not a clean A/B on the series alone. Scope: RGB output only (the YUV420 output series is separate), no USB-C DP on this base, VC4 side not exercised. Igor