Re: [PATCH v6 01/12] dt-bindings: reserved-memory: Document Tegra VPR

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The examples fail to provide a `reserved-memory` parent node to establish the `#address-cells` and `#size-cells` context, leading to schema validation failures.
--

commit f2d3906971093a4dcbac5c42465c2d0d7ce5d0a8
Author: Thierry Reding <treding@nvidia.com>

dt-bindings: reserved-memory: Document Tegra VPR

This commit adds device tree bindings for the NVIDIA Tegra Video Protection
Region (VPR), documenting both fixed and resizable variants.

> diff --git a/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra-video-protection-region.yaml b/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra-video-protection-region.yaml
> new file mode 100644
> index 0000000000000..862bfd3913786
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra-video-protection-region.yaml

[ ... ]

> +examples:
> +  - |
> +    /* resizable VPR */
> +    protected {
> +      compatible = "nvidia,tegra-video-protection-region";
> +
> +      size = <0x0 0x70000000>;

[Severity: Low]
Will this fail make dt_binding_check during schema validation?

Since the example lacks an explicit reserved-memory parent node to establish
the #address-cells and #size-cells context, dtschema wraps this in a dummy
root node with a default of #size-cells = <1>. Supplying 2 cells for the
size here exceeds that implicit constraint.

> +      alignment = <0x0 0x100000>;

[Severity: Low]
Similarly, does this 2-cell alignment array violate the implicit
#size-cells = <1> constraint for the same reason?

> +      reusable;
> +    };
> +
> +  - |
> +    /* fixed VPR */
> +    protected@a8000000 {
> +      compatible = "nvidia,tegra-video-protection-region";
> +
> +      /* fixed VPR */
> +      reg = <0xa8000000 0x70000000>;

[Severity: Low]
Without a shared parent node to explicitly declare #address-cells and
#size-cells contexts, does this 2-cell reg property parse under the default
1-cell context (treating address=0xa8000000 and size=0x70000000)?

This creates a semantic mismatch with the 64-bit lengths intended in the
first example. Wrapping the examples in a reserved-memory parent node might
resolve these context issues.

> +      no-map;
> +    };

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260904-tegra-vpr-v6-0-79042cfa8de5@nvidia.com?part=1