Re: [PATCH 14/17] phy: qcom: edp: Add Nord PLL configuration callback

[sashiko-bot@kernel.org]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [High] The PLL configuration incorrectly writes 0x1d to DP_QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN, silently overwriting the 0x1f value set during initialization.
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commit 16052638682492657891d8a92561073f1ca35358
Author: Ritesh Kumar <ritesh.kumar@oss.qualcomm.com>

phy: qcom: edp: Add Nord PLL configuration callback

Nord uses a 38.4 MHz CXO reference with a different QSERDES v8 COM register
layout and PLL coefficients. This commit adds a configuration callback to
program the QSERDES COM PLL registers with link-rate-dependent values.

> diff --git a/drivers/phy/qualcomm/phy-qcom-edp.c b/drivers/phy/qualcomm/phy-qcom-edp.c
> index a0f4b12e561e9..4d1b2c81d9563 100644
> --- a/drivers/phy/qualcomm/phy-qcom-edp.c
> +++ b/drivers/phy/qualcomm/phy-qcom-edp.c
[ ... ]
> @@ -1688,6 +1688,118 @@ static int qcom_edp_com_configure_ssc_nord(const struct qcom_edp *edp)
[ ... ]
> +static int qcom_edp_com_configure_pll_nord(const struct qcom_edp *edp)
> +{
[ ... ]
> +	writel(0x0a, edp->pll + DP_QSERDES_V8_COM_BG_TIMER);
> +	writel(core_clk_div_mode0, edp->pll + DP_QSERDES_V8_COM_CORECLK_DIV_MODE0);
> +	writel(0x00, edp->pll + DP_QSERDES_V8_COM_VCO_TUNE_CTRL);
> +	writel(0x1d, edp->pll + DP_QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN);

[Severity: High]
Will this unconditional write of 0x1d silently overwrite the 0x1f bias enable
value required and set during PHY initialization?

It looks like qcom_edp_phy_init() calls com_bias_en_clkbuflr_nord() to set
this register to 0x1f. Later, when qcom_edp_phy_power_on() calls
com_configure_pll_nord(), this exact register is overwritten with 0x1d.

Could clearing this bit (bit 1) prevent the PLL from locking or cause link
training failures resulting in a blank display?

> +	writel(0x0f, edp->pll + DP_QSERDES_V8_COM_CORE_CLK_EN);
> +	writel(code1_mode0, edp->pll + DP_QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0);
> +	writel(code2_mode0, edp->pll + DP_QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0);
> +
> +	return 0;
> +}
[ ... ]

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Sashiko AI review · https://sashiko.dev/#/patchset/20260911-nord-drv-dt-v1-0-e25c073cf1b6@oss.qualcomm.com?part=14