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[2001:4c4e:1b91:8f00:f78d:5b18:1090:144b]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49e60ac42b9sm97156775e9.6.2026.09.11.12.29.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 11 Sep 2026 12:29:17 -0700 (PDT) From: Igor Paunovic To: Jiaxing Hu Cc: Tomeu Vizoso , linux-rockchip@lists.infradead.org, dri-devel@lists.freedesktop.org, Igor Paunovic Subject: Re: [PATCH v10 00/13] accel/rocket: RK3576 NPU (RKNN) enablement Date: Fri, 11 Sep 2026 21:28:32 +0200 Message-ID: <20260911192833.105634-1-royalnet026@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260911122832.1364839-1-gahing@gahingwoo.com> References: <20260831040804.24111-1-gahing@gahingwoo.com> <20260911122832.1364839-1-gahing@gahingwoo.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi Jiaxing, Thanks for going back over it, but the correction needs one more turn: both sets of numbers are mine, from two different days. The 45 (12 + 8 + 12 + 13) is the 19 August A/B square on v8 1-2/12 [1]: no manifestation on either arm, oracle 48/48 throughout. That is what the patch text describes, and it is right. The 102 is the 25 August re-run on v9 as posted [2]: v9 arm 12 + 11 resets, all 48/48; differential arm (same base, 1/13 and 2/13 removed) five runs, 8/10/12/8/15; plus 13 + 13 on a third arm with 3/13 added [3]. In one of the five differential runs the inference issued after the forced autosuspend/resume "succeeded" and returned all 48 output channels at 0x80 while the CPU reference varied normally, with nothing in dmesg, lockdep or on the serial console. That run was on RK3588, on my board, and the v10 cover quoted it as I wrote it. So the signature is shared, not carried over. Your explanation of it (fresh shmem BO zeroed, teflon readback adding 0x80) is the same mechanism I inferred from the scorer, which flagged 128 as not this model's zero point, i.e. an output buffer that was never written. What holds is the caveat I put on it then: one event in 53 differential resets, zero in 49 with the patches, timing-dependent, and my protocol cannot tell a genuinely hung block from a lost completion. It bounds; it does not prove. The artifacts (scorer output, runtime and genpd state, journal, serial log) are preserved if you or Tomeu want them. If you respin, both statements can stand next to each other: 45 resets with no manifestation on 19 August, and one silent completion on the unpatched arm out of 102 resets on 25 August. [1] https://lore.kernel.org/all/20260819073530.6087-1-royalnet026@gmail.com/ [2] https://lore.kernel.org/all/CAEWPSH5mxTbUkNouxm6yecMZYvDowquhvYvhaXQ8HoMtHD5U1g@mail.gmail.com/ [3] https://lore.kernel.org/all/CAEWPSH5MVzoQMaFOEQ93+1pOPmcXCDNfuXsv5j-X8Lb1fy_hrg@mail.gmail.com/ Regards, Igor