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([85.233.101.104]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49fc56aab7csm168250455e9.1.2026.09.20.12.39.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 20 Sep 2026 12:39:47 -0700 (PDT) From: Leander Kieweg To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Cc: airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, u.kleine-koenig@baylibre.com, Leander Kieweg Subject: [PATCH v5 0/2] drm: Add DRM driver for GlandaGPU (VHDL soft-IP GPU) Date: Sun, 20 Sep 2026 21:39:42 +0200 Message-ID: <20260920193944.110983-1-kieweg.leander@gmail.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" This is v5 of the GlandaGPU DRM driver series [1][2][3][4]. It addresses review feedback from Thomas Zimmermann and the automated review bot on v4. GlandaGPU is a small VHDL soft-IP 2D display controller, currently targeting a Terasic DE10-Standard (Cyclone V SoC). This series has been tested against a QEMU digital twin and on real hardware. Hardware/VHDL: https://github.com/stiangglanda/GlandaGPU QEMU fork: https://github.com/stiangglanda/qemu-glandagpu Userspace tests: https://github.com/stiangglanda/GlandaGPU-userspace-tests Changes since v4: dt-bindings: - Mark "interrupts" as required in kieweg,gpu.yaml, now that the IRQ is a hard requirement for the driver. driver core: - Replace iosys_map_rd() in glanda_blit_rect() with iosys_map_memcpy_from() into a per-row scratch buffer allocated via drm_format_conv_state_reserve() (solves the unaligned-pitch problem without breaking uAPI) (Thomas Zimmermann). - Add drm_atomic_helper_shutdown() to glanda_drm_fini(), after drm_dev_unplug() (Thomas Zimmermann). - Add an all-ones check in glanda_irq_handler() to guard against a disconnected/floating ISR register (Sashiko bot). - Add .shutdown for both the platform driver and the PCI driver (Sashiko bot). The Sashiko bot also flagged drm_gem_fb_begin_cpu_access() and drm_gem_fb_end_cpu_access() as potentially sleeping in atomic context. I'm keeping these as they are, since they were added on Thomas' recommendation in the first place. Regarding IRQ handling: as Thomas suggested, I made the IRQ a hard requirement and removed the polling fallback entirely. That fallback was legacy from an earlier hardware revision that didn't support IRQs at all. Since current hardware always has one, keeping two code paths around wasn't worth the maintenance cost. Because of this, I also had to mark "interrupts" as required in the kieweg,gpu.yaml dt-binding again. That patch already carried a Reviewed-by from Krzysztof Kozlowski in v4, but since the binding changed, I'm not carrying that tag forward this time. [1] v1: https://lore.kernel.org/dri-devel/20260714101146.200416-1-kieweg.leander@gmail.com/T/#t [2] v2: https://lore.kernel.org/dri-devel/20260730173643.256052-1-kieweg.leander@gmail.com/T/#t [3] v3: https://lore.kernel.org/dri-devel/20260824195418.17707-1-kieweg.leander@gmail.com/T/#t [4] v4: https://lore.kernel.org/dri-devel/20260913205007.118552-1-kieweg.leander@gmail.com/T/#t Leander Kieweg (2): dt-bindings: display: Add GlandaGPU binding drm/glanda: Add initial DRM driver for GlandaGPU .../bindings/display/kieweg,gpu.yaml | 56 ++ .../devicetree/bindings/vendor-prefixes.yaml | 2 + MAINTAINERS | 6 + drivers/gpu/drm/tiny/Kconfig | 11 + drivers/gpu/drm/tiny/Makefile | 1 + drivers/gpu/drm/tiny/glandagpu.c | 655 ++++++++++++++++++ 6 files changed, 731 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/kieweg,gpu.yaml create mode 100644 drivers/gpu/drm/tiny/glandagpu.c -- 2.43.0