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[2001:4c4e:1b80:5300:5697:1c62:8020:2175]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49fdaaf97e2sm18248625e9.2.2026.09.22.01.01.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2026 01:01:33 -0700 (PDT) From: Igor Paunovic To: Tomeu Vizoso , Oded Gabbay , Heiko Stuebner Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jeff Hugo , Robert Foss , Sidong Yang , Diederik de Haas , Sebastian Reichel , Jiaxing Hu , Nicolas Dufresne , Jonas Karlman , Guangshuo Li , =?UTF-8?q?H=C3=BCseyin=20BIYIK?= , dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Igor Paunovic Subject: [PATCH v2 06/11] dt-bindings: npu: rockchip: allow DVFS and thermal properties Date: Tue, 22 Sep 2026 10:01:09 +0200 Message-ID: <20260922080114.44662-7-royalnet026@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260922080114.44662-1-royalnet026@gmail.com> References: <20260922080114.44662-1-royalnet026@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The three NPU cores on the RK3588 are fed by a single clock and a single supply, and the firmware accepts a fixed set of rates for that clock. Describing those rates as an operating-points-v2 table is what lets a driver scale the NPU instead of leaving it at whatever rate the bootloader set, so allow the property on the core node. Throttling the NPU from a thermal zone needs a core node to be usable as a cooling device, so allow #cooling-cells too. The OPP table belongs on every core, with opp-shared: the cores have no clock of their own, and one shared table for one shared clock is the same shape a CPU cluster uses. #cooling-cells goes on one core only, the one a thermal zone's cooling map names, because the cores cannot be throttled independently. Naming one representative node for a shared frequency domain is the established shape, as in "Cpufreq cooling device on CPU0" in Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml. The schema cannot enforce which core carries #cooling-cells, because all three cores share a compatible string and a node name pattern, so that stays a devicetree convention. That is the same situation as for CPU cooling, where cpus.yaml does not restrict #cooling-cells to cpu@0 either. The example gains #cooling-cells; the operating-points-v2 property is exercised by the RK3588 devicetree later in this series. Assisted-by: LLM checkpatch dt_binding_check Signed-off-by: Igor Paunovic Acked-by: Conor Dooley --- v2: the text on where the properties go is rewritten for opp-shared on all three cores, following Nicolas Dufresne's review of v1 3/7. The only change to the schema file is the wording of the #cooling-cells description; the constraints and the example are unchanged. Conor, your Ack is kept on that basis; please say if it no longer holds. .../bindings/npu/rockchip,rk3588-rknn-core.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml index caca2a4903cd1..beba1896156f5 100644 --- a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml +++ b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml @@ -42,6 +42,13 @@ properties: - const: npu - const: pclk + "#cooling-cells": + description: + Present on one core only, the first, which stands for the shared NPU + clock as a cooling device. The other cores have no clock of their own + and cannot be throttled independently of it. + const: 2 + interrupts: maxItems: 1 @@ -50,6 +57,8 @@ properties: npu-supply: true + operating-points-v2: true + power-domains: maxItems: 1 @@ -100,6 +109,7 @@ examples: clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>, <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>; clock-names = "aclk", "hclk", "npu", "pclk"; + #cooling-cells = <2>; interrupts = ; iommus = <&rknn_mmu_0>; npu-supply = <&vdd_npu_s0>; -- 2.43.0