From: sashiko-bot@kernel.org
To: "Hamin Sung" <hamin@saltyming.net>
Cc: dri-devel@lists.freedesktop.org
Subject: Re: [RFC PATCH 1/2] drm/nouveau/pmu/gt215: add graphics engine load counters
Date: Sat, 03 Oct 2026 23:57:46 +0000 [thread overview]
Message-ID: <20261003235746.EDA741F0089B@smtp.kernel.org> (raw)
In-Reply-To: <20261003234520.69573-1-hamin@saltyming.net>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] drm/nouveau/pmu: non-atomic counter read-and-reset causes PMU cycle loss
--
commit b1f69f3978548eb48a40027083a2b64535b82115
Author: Hamin Sung <hamin@saltyming.net>
drm/nouveau/pmu/gt215: add graphics engine load counters
This commit adds initialization and read functions for the PDAEMON idle
counters on GT215 and related GPUs. The counters track PMU clock cycles and
graphics engine busy cycles, returning and clearing the values when read.
Link: https://envytools.readthedocs.io/en/latest/hw/pm/pdaemon/counter.html
> diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c
> index 32cee21ed8585..37310a8ebe818 100644
> --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c
> +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.c
[ ... ]
> @@ -260,6 +260,44 @@ gt215_pmu_init(struct nvkm_pmu *pmu)
> +static void
> +gt215_pmu_perfmon_read(struct nvkm_pmu *pmu, u32 *busy, u32 *total)
> +{
> + struct nvkm_device *device = pmu->subdev.device;
> +
> + *busy = nvkm_rd32(device, 0x10a508 + GT215_PMU_COUNTER_GR * 0x10);
> + *total = nvkm_rd32(device, 0x10a508 + GT215_PMU_COUNTER_TOTAL * 0x10);
> + nvkm_wr32(device, 0x10a508 + GT215_PMU_COUNTER_GR * 0x10, 0x80000000);
> + nvkm_wr32(device, 0x10a508 + GT215_PMU_COUNTER_TOTAL * 0x10, 0x80000000);
[Severity: Medium]
Does this non-atomic counter read-and-reset sequence cause PMU cycle loss?
If a hardware interrupt or CPU preemption occurs between reading the
counters and writing the reset values, any hardware cycles that elapse
during that window are permanently lost from the statistics.
Additionally, a delay between the two reset writes can skew the intervals,
which could result in the busy count exceeding the total count.
A review of the follow-up devfreq patch shows that the caller gracefully
handles the invariant breakage:
if (total && busy <= total)
...
else
stat->busy_time = stat->total_time;
This mitigates the risk of integer underflow or metrics exceeding 100%.
However, it handles the symptom rather than preventing the permanent
loss of PMU cycles during the unprotected preemption window.
> +
> + *busy &= 0x7fffffff;
> + *total &= 0x7fffffff;
> +}
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261003223420.77993-1-hamin@saltyming.net?part=1
next prev parent reply other threads:[~2026-10-03 23:57 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-03 22:34 [RFC PATCH 0/2] drm/nouveau: select GT21x performance levels by load through devfreq Hamin Sung
2026-10-03 23:45 ` [RFC PATCH 1/2] drm/nouveau/pmu/gt215: add graphics engine load counters Hamin Sung
2026-10-03 23:57 ` sashiko-bot [this message]
2026-10-03 23:45 ` [RFC PATCH 2/2] drm/nouveau: select GT21x performance levels by load through devfreq Hamin Sung
2026-10-03 23:50 ` [RFC PATCH 0/2] " Lyude Paul
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