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Svyatoslav Ryhel Cc: Thierry Reding , Thierry Reding , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mauro Carvalho Chehab , Greg Kroah-Hartman , Dmitry Osipenko , Charan Pedumuru , linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Subject: Re: [PATCH v1 01/19] clk: tegra: init CSUS clock for Tegra20 and Tegra30 Date: Thu, 28 Aug 2025 19:15:38 +0900 Message-ID: <2263218.C4sosBPzcN@senjougahara> In-Reply-To: References: <20250819121631.84280-1-clamor95@gmail.com> <1797126.QkHrqEjB74@senjougahara> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-ClientProxiedBy: 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Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Thursday, August 28, 2025 5:28=E2=80=AFPM Svyatoslav Ryhel wrote: > =D1=87=D1=82, 28 =D1=81=D0=B5=D1=80=D0=BF. 2025=E2=80=AF=D1=80. =D0=BE 11= :13 Mikko Perttunen =D0=BF=D0=B8=D1=88=D0=B5: > > On Wednesday, August 27, 2025 7:45=E2=80=AFPM Svyatoslav Ryhel wrote: > > > =D1=81=D1=80, 27 =D1=81=D0=B5=D1=80=D0=BF. 2025=E2=80=AF=D1=80. =D0= =BE 13:36 Mikko Perttunen =20 =D0=BF=D0=B8=D1=88=D0=B5: > > > > On Wednesday, August 27, 2025 1:32=E2=80=AFPM Svyatoslav wrote: > > > > > 27 =D1=81=D0=B5=D1=80=D0=BF=D0=BD=D1=8F 2025=E2=80=AF=D1=80. 07:0= 9:45 GMT+03:00, Mikko Perttunen > > > >=20 > > > > =D0=BF=D0=B8=D1=88=D0=B5: > > > > > >On Tuesday, August 19, 2025 9:16=E2=80=AFPM Svyatoslav Ryhel wro= te: > > > > > >> CSUS clock is required to be enabled on camera device > > > > > >> configuration > > > > > >> or > > > > > >> else camera module refuses to initiate properly. > > > > > >>=20 > > > > > >> Signed-off-by: Svyatoslav Ryhel > > > > > >> --- > > > > > >>=20 > > > > > >> drivers/clk/tegra/clk-tegra20.c | 1 + > > > > > >> drivers/clk/tegra/clk-tegra30.c | 1 + > > > > > >> 2 files changed, 2 insertions(+) > > > > > >>=20 > > > > > >> diff --git a/drivers/clk/tegra/clk-tegra20.c > > > > > >> b/drivers/clk/tegra/clk-tegra20.c index > > > > > >> 551ef0cf0c9a..42f8150c6110 > > > > > >> 100644 > > > > > >> --- a/drivers/clk/tegra/clk-tegra20.c > > > > > >> +++ b/drivers/clk/tegra/clk-tegra20.c > > > > > >> @@ -1043,6 +1043,7 @@ static struct tegra_clk_init_table > > > > > >> init_table[] > > > > > >> =3D { > > > > > >>=20 > > > > > >> { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 }, > > > > > >> { TEGRA20_CLK_VDE, TEGRA20_CLK_PLL_C, 300000000, 0 }, > > > > > >> { TEGRA20_CLK_PWM, TEGRA20_CLK_PLL_P, 48000000, 0 }, > > > > > >>=20 > > > > > >> + { TEGRA20_CLK_CSUS, TEGRA20_CLK_CLK_MAX, 6000000, 1 }, > > > > > >>=20 > > > > > >> /* must be the last entry */ > > > > > >> { TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 }, > > > > > >> =20 > > > > > >> }; > > > > > >>=20 > > > > > >> diff --git a/drivers/clk/tegra/clk-tegra30.c > > > > > >> b/drivers/clk/tegra/clk-tegra30.c index > > > > > >> 82a8cb9545eb..70e85e2949e0 > > > > > >> 100644 > > > > > >> --- a/drivers/clk/tegra/clk-tegra30.c > > > > > >> +++ b/drivers/clk/tegra/clk-tegra30.c > > > > > >> @@ -1237,6 +1237,7 @@ static struct tegra_clk_init_table > > > > > >> init_table[] > > > > > >> =3D { > > > > > >>=20 > > > > > >> { TEGRA30_CLK_HDA, TEGRA30_CLK_PLL_P, 102000000, 0 }, > > > > > >> { TEGRA30_CLK_HDA2CODEC_2X, TEGRA30_CLK_PLL_P, 48000000, 0 = }, > > > > > >> { TEGRA30_CLK_PWM, TEGRA30_CLK_PLL_P, 48000000, 0 }, > > > > > >>=20 > > > > > >> + { TEGRA30_CLK_CSUS, TEGRA30_CLK_CLK_MAX, 6000000, 1 }, > > > > > >>=20 > > > > > >> /* must be the last entry */ > > > > > >> { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 }, > > > > > >> =20 > > > > > >> }; > > > > > > > > > > > >I looked into what this clock does and it seems to be a gate for > > > > > >the > > > > > >CSUS > > > > > >pin, which provides an output clock for camera sensors (VI MCLK)= . > > > > > >Default > > > > > >source seems to be PLLC_OUT1. It would be good to note that on t= he > > > > > >commit > > > > > >message, as I can't find any documentation about the CSUS clock > > > > > >elsewhere. > > > > > > > > > > > >What is the 6MHz rate based on? > > > > >=20 > > > > > 6mhz is the statistic value which I was not able to alter while > > > > > testing. > > > > > I > > > > > have tried 12mhz and 24mhz too but it remained 6mhz, so I left it > > > > > 6mhz. > > > > >=20 > > > > > >Since this seems to be a clock consumed by the sensor, it seems = to > > > > > >me > > > > > >that > > > > > >rather than making it always on, we could point to it in the > > > > > >sensor's > > > > > >device tree entry. > > > > >=20 > > > > > Sensor device tree uses vi_sensor as clocks source and sensor > > > > > drivers > > > > > don't > > > > > support multiple linked clocks. > > > >=20 > > > > AIUI vi_sensor is an internal clock so the sensor cannot be receivi= ng > > > > it > > > > directly. Perhaps the sensor is actually connected to csus, and the > > > > reason > > > > we need to enable it is to allow the vi_sensor clock to pass throug= h > > > > the > > > > csus gate? > > > >=20 > > > > That leaves the question of why the csus pad would be muxed to > > > > vi_sensor > > > > by > > > > default, but perhaps there's an explanation for that. > > >=20 > > > From downstream T30 sources csus and vi_sensor are always called in > > > pair (6MHz csus and 24MHz for vi_sensor), naturally I assumed that > > > latter is used as camera reference clock since most sensors has > > > reference clock around 24 MHz > >=20 > > It's possible that the csus pad is still outputting 24MHz. The pinmux > > options for the csus pad are various clocks, so it would seem logical > > that the clock source for the pad is one of those clocks. However, on t= he > > clock framework side, the csus clock is just a gate. What I'm confused > > about is that since on the clock framework side the parent of csus is > > currently set to clk_m, I don't know why setting the rate of csus would > > affect the output of the pad, given clk_m is not one of the options for > > the pinmux. > >=20 > > It's be good to verify the register value for the csus pinmux to see wh= ere > > it thinks the clock is coming from, and then check how that matches wit= h > > what we are seeing. >=20 > TRM does not provide such data, it has only register address with > layout for it as a plain pad control, that register has only DRVDN, > DRVUP, SLWR and SLWF and I don't see a way to decode clock value or > parent or anything similar. If you give me a method I will calculate > those values. I notice that on Tegra20, there is a mux pingroup called 'csus', which has = the=20 mux options PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, and VI_SENSOR_CLK (based on=20 upstream pinctrl-tegra20.c). The TRM also says 'Enable clock to SUS pad.'=20 about the CSUS (or SUS) clock. On Tegra30, however, which I guess you refer to, I guess mux pingroups are= =20 gone and each pin has its own mux (again looking at upstream pinctrl- tegra30.c). vi_mclk_pt1 is now its own mux with the options VI, VI_ALT1,=20 VI_ALT2, VI_ALT3. The drive group for this pin is still called csus, so by= =20 that name it only has the drive settings as you mention. Are you testing on Tegra20, Tegra30, or both? I've looked at some Tegra30 schematics, and they show a signal called VI_MC= LK=20 being routed to CSI cameras. >=20 > Another theory is that maybe csus is used for VIP cameras only and > vi_sensor is used for CSI cameras, but they both have to be on in > order to work correctly. Csus was removed from Tegra114 along with > VIP, might not be a coincidence. Moreover, T124 uses vi_sensor as > camera mclk source. I see the CSUS clock still on Tegra124 based on the upstream kernel. There = is=20 also a CAM_MCLK pin. It seems Tegra30 has both VI_MCLK and CAM_MCLK pins,=20 which both can output the clock. After Tegra30 there is only CAM_MCLK. Looking at L4T r21, in tegra12_clocks.c, it defines the clocks mclk and mcl= k2.=20 There is a comment on mclk saying: .clk_num =3D 92, /* csus */ whereas mclk2 is vim2_clk. These clocks are indeed defined as gates, with=20 vi_sensor / vi_sensor2 as parent, set_rate being passed onto the parent. All of that wasn't very coherently written, but to summarize my thoughts: On Tegra30, we have - Pins vi_mclk and cam_mclk. Both can only source from (vi_)mclk which also= =20 goes by name csus. The mclk/csus clock is a clock gate with vi_sensor as=20 parent. On Tegra114 and later, - Same situation, but vi_mclk is gone, so instead we have cam_mclk (possibl= y=20 multiple with associated mclkN and vi_sensorN clocks) On Tegra20, - The vi_mclk pin has a variety of mux options, one of which is VI_SENSOR_C= LK.=20 I expect this to correspond to the same behavior as later chips, i.e. sourc= es=20 from the csus(/mclk) clock, which sources from vi_sensor. >=20 > Here is a fragment of Tegra124 clock tree (dumped from Mi pad 1) >=20 > pll_p on 13 x34 408000= 000 > vi_sensor2 $ off 0 3.0 136000000 mclk2 = =20 > $ off 0 136000000 vi_sensor = =20 > $ off 0 3.0 136000000 mclk $ o= ff > 0 136000000 > > > > > >Cheers, > > > > > >Mikko