Re: [PATCH] drm/i915/dsi: Do not clear DPOUNIT_CLOCK_GATE_DISABLE from vlv_init_display_clock_gating

From: Hans de Goede <hdegoede@redhat.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: intel-gfx <intel-gfx@lists.freedesktop.org>,
	dri-devel@lists.freedesktop.org, stable@vger.kernel.org,
	Dave Airlie <airlied@redhat.com>,
	Daniel Vetter <daniel.vetter@intel.com>
Subject: Re: [PATCH] drm/i915/dsi: Do not clear DPOUNIT_CLOCK_GATE_DISABLE from vlv_init_display_clock_gating
Date: Fri, 2 Dec 2016 14:27:43 +0100	[thread overview]
Message-ID: <267c1873-d135-7b27-e9f6-c8e8663cd011@redhat.com> (raw)
In-Reply-To: <20161202124054.GU31595@intel.com>

Hi,

On 02-12-16 13:40, Ville Syrjälä wrote:
> On Thu, Dec 01, 2016 at 04:39:57PM +0100, Hans de Goede wrote:
>> On my Cherrytrail CUBE iwork8 Air tablet PIPE-A would get stuck on loading
>> i915 at boot 1 out of every 3 boots, resulting in a non functional LCD.
>> Once the i915 driver has successfully loaded, the panel can be disabled /
>> enabled without hitting this issue.
>>
>> The getting stuck is caused by vlv_init_display_clock_gating() clearing
>> the DPOUNIT_CLOCK_GATE_DISABLE bit in DSPCLK_GATE_D when called from
>> chv_pipe_power_well_ops.enable() on driver load, while PIPE-A is enabled
>> driving the DSI LCD by the BIOS.
>>
>> Clearing this bit while DSI is in use is a known issue and
>> intel_dsi_pre_enable() / intel_dsi_post_disable() already set / clear it
>> as appropriate.
>>
>> This commit modifies vlv_init_display_clock_gating() to leave the
>> DPOUNIT_CLOCK_GATE_DISABLE bit alone fixing PIPE-A getting stuck.
>>
>> BugLink: https://bugs.freedesktop.org/show_bug.cgi?id=97330
>> Cc: stable@vger.kernel.org
>> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
>> ---
>>  drivers/gpu/drm/i915/intel_runtime_pm.c | 13 ++++++++++++-
>>  1 file changed, 12 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
>> index 356c662..b5ce7cb 100644
>> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
>> @@ -1039,7 +1039,18 @@ static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
>>
>>  static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
>>  {
>> -	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
>> +	u32 val;
>> +
>> +	/*
>> +	 * When on driver load, PIPE A may be active and driving a DSI display.
>> +	 * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid PIPE A getting stuck
>> +	 * (and never recovering) in this case. intel_dsi_post_disable() will
>> +	 * clear it when we turn off the display.
>
> Why are you talking only about pipe A here?

Because that is the pipe which was getting stuck on my tablet. I see that
the comment for the same workaround in intel_dsi.c just says:
" Disable DPOunit clock gating, can stall pipe" so I guess I should
update the comment s/PIPE A/pipe(s)/. Any other remarks before I send a v2 ?

Regards,

Hans

>
>> +	 */
>> +	val = I915_READ(DSPCLK_GATE_D);
>> +	val &= DPOUNIT_CLOCK_GATE_DISABLE;
>> +	val |= VRHUNIT_CLOCK_GATE_DISABLE;
>> +	I915_WRITE(DSPCLK_GATE_D, val);
>>
>>  	/*
>>  	 * Disable trickle feed and enable pnd deadline calculation
>> --
>> 2.9.3
>>
>> _______________________________________________
>> dri-devel mailing list
>> dri-devel@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel