From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ECAFAC7EE2A for ; Wed, 25 Jun 2025 14:41:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 508AF10E73D; Wed, 25 Jun 2025 14:41:43 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="RPTkFSpG"; dkim-atps=neutral Received: from tor.source.kernel.org (tor.source.kernel.org [172.105.4.254]) by gabe.freedesktop.org (Postfix) with ESMTPS id CA01310E73D for ; Wed, 25 Jun 2025 14:41:41 +0000 (UTC) Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id C989760010; Wed, 25 Jun 2025 14:41:37 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4C3CAC4CEEA; Wed, 25 Jun 2025 14:41:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1750862497; bh=G6puNagQFSMyUjbE+LIXearsZJYWlEPDrvFoYitM1po=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=RPTkFSpGXwsznlbnK1kUH0xY734FEMB9huWys+Ev9Cd+4RJT8ipohTvGXg1+rNrW2 xZXfCYR8VgiqpycgDQJU81jj7xQmtcM7lUCtaXdTKEsFK07SBk0DaA58xdjAtQT/0f ErLdmRUotPrLCgcHkamQUiCRjkBx+tzhoSM6XbZ0szoBmgSrosAW8TAg6NPWKtKGyR 7BtssmQmLb903HrvtT6vIoSUszrN5gfh8b46F9KOoPTmVlI1Rg8AbfNLeSEmq4iE5o wyhdS1BfCk4M1YjE+no4eesqtrBibQTlgAk4QmmTo/CGP2ZO4DNpPZontcAgGNLi4O gq/YUuVWNzbWQ== Message-ID: <27068fd3-92b5-402b-9f3c-fd786db56668@kernel.org> Date: Wed, 25 Jun 2025 16:41:28 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 5/8] dt-bindings: gpu: img,powervr-rogue: Add TH1520 GPU compatible To: Michal Wilczynski , Matt Coster Cc: Drew Fustini , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Philipp Zabel , Frank Binns , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Ulf Hansson , Marek Szyprowski , Krzysztof Kozlowski , Bartosz Golaszewski , "linux-riscv@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-pm@vger.kernel.org" , "dri-devel@lists.freedesktop.org" References: <20250623-apr_14_for_sending-v6-0-6583ce0f6c25@samsung.com> <20250623-apr_14_for_sending-v6-5-6583ce0f6c25@samsung.com> <9c82a6bc-c6ff-4656-8f60-9d5fa499b61a@imgtec.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 25/06/2025 16:18, Michal Wilczynski wrote: > > > On 6/25/25 15:55, Krzysztof Kozlowski wrote: >> On 25/06/2025 14:45, Michal Wilczynski wrote: >>> >>> >>> On 6/24/25 15:53, Matt Coster wrote: >>>> On 23/06/2025 12:42, Michal Wilczynski wrote: >>>>> Update the img,powervr-rogue.yaml to include the T-HEAD TH1520 SoC's >>>>> specific GPU compatible string. >>>>> >>>>> The thead,th1520-gpu compatible, along with its full chain >>>>> img,img-bxm-4-64, and img,img-rogue, is added to the >>>>> list of recognized GPU types. >>>>> >>>>> The power-domains property requirement for img,img-bxm-4-64 is also >>>>> ensured by adding it to the relevant allOf condition. >>>>> >>>>> Acked-by: Krzysztof Kozlowski >>>>> Reviewed-by: Ulf Hansson >>>>> Reviewed-by: Bartosz Golaszewski >>>>> Signed-off-by: Michal Wilczynski >>>>> --- >>>>> Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml | 9 ++++++++- >>>>> 1 file changed, 8 insertions(+), 1 deletion(-) >>>>> >>>>> diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml >>>>> index 4450e2e73b3ccf74d29f0e31e2e6687d7cbe5d65..9b241a0c1f5941dc58a1e23970f6d3773d427c22 100644 >>>>> --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml >>>>> +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml >>>>> @@ -21,6 +21,11 @@ properties: >>>>> # work with newer dts. >>>>> - const: img,img-axe >>>>> - const: img,img-rogue >>>>> + - items: >>>>> + - enum: >>>>> + - thead,th1520-gpu >>>>> + - const: img,img-bxm-4-64 >>>>> + - const: img,img-rogue >>>>> - items: >>>>> - enum: >>>>> - ti,j721s2-gpu >>>>> @@ -93,7 +98,9 @@ allOf: >>>>> properties: >>>>> compatible: >>>>> contains: >>>>> - const: img,img-axe-1-16m >>>>> + enum: >>>>> + - img,img-axe-1-16m >>>>> + - img,img-bxm-4-64 >>>> >>>> This isn't right – BXM-4-64 has two power domains like BXS-4-64. I don't >>>> really know what the right way to handle that in devicetree is given the >>>> TH1520 appears to expose only a top-level domain for the entire GPU, but >>>> there are definitely two separate domains underneath that as far as the >>>> GPU is concerned (see the attached snippet from integration guide). >>>> >>>> Since power nodes are ref-counted anyway, do we just use the same node >>>> for both domains and let the driver up/down-count it twice? >>> >>> Hi Matt, >>> >>> Thanks for the very helpful insight. That's a great point, it seems the >>> SoC's design presents a tricky case for the bindings. >>> >>> I see what you mean about potentially using the same power domain node >>> twice. My only hesitation is that it might be a bit unclear for someone >>> reading the devicetree later. Perhaps another option could be to relax >>> the constraint for this compatible? >>> >>> Krzysztof, we'd be grateful for your thoughts on how to best model this >>> situation. >> >> >> It's your hardware, you should tell us, not me. I don't know how many >> power domains you have there, but for sure it is not one AND two domains >> the same time. It is either one or two, because power domains are not >> the same as regulator supplies. > > Hi Krzysztof, Matt, > > The img,bxm-4-64 GPU IP itself is designed with two separate power > domains. The TH1520 SoC, which integrates this GPU, wires both of these > to a single OS controllable power gate (controlled via mailbox and E902 > co-processor). This helps... and also sounds a lot like regulator supplies, not power domains. :/ > > This means a devicetree for the TH1520 can only ever provide one power > domain for the GPU. However, a generic binding for img,bxm-4-64 should If this was a supply, you would have two supplies. Anyway internal wirings of GPU do not matter in such case and more important what the SoC has wired. And it has one power domain. > account for a future SoC that might implement both power domains. > > That's why I proposed to relax the constraints on the img,bmx-4-64 GPU. This should be constrained per each device, so 1 for you and 2 for everyone else. Best regards, Krzysztof