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Sat, 08 Aug 2026 07:29:29 -0700 (PDT) Received: from localhost ([2403:2c80:17:1e::20db]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84f5a3cad9dsm2140077b3a.23.2026.08.08.07.29.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 08 Aug 2026 07:29:28 -0700 (PDT) Date: Sat, 08 Aug 2026 22:29:25 +0800 Message-ID: <2b3c661bf7e1d437f81e4b7da13be25d.codykang.hk@gmail.com> From: Cody Kang To: Rob Herring Cc: David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Vinod Koul , Neil Armstrong , Haylen Chu , Michael Turquette , Stephen Boyd , Brian Masney , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , dri-devel@lists.freedesktop.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, spacemit@lists.linux.dev, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-clk@vger.kernel.org Subject: Re: [PATCH RESEND 04/17] dt-bindings: soc: spacemit: allow eDP/DP PHY PLL pixel clocks on K3 APMU In-Reply-To: <20260807230824.GA2220945-robh@kernel.org> References: <20260725-k3-display-v1-0-6de34d80e86c@gmail.com> <20260725-k3-display-v1-4-6de34d80e86c@gmail.com> <20260807230824.GA2220945-robh@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-Mailman-Approved-At: Mon, 10 Aug 2026 06:37:47 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi Rob, On Fri, 07 Aug 2026 18:08:24 -0500, Rob Herring wrote: > On Sat, Jul 25, 2026 at 12:51:13AM -0400, Cody Kang wrote: > > The APMU's eDP pixel-clock muxes select the DP PHY PLLs as parents, so the > > K3 syscon takes two clock inputs the other variants do not have. > > > > Gate them behind the K3 compatible instead of widening the shared clock > > list, so a non-K3 syscon cannot silently accept clocks it has no mux for. > > > > Signed-off-by: Cody Kang > > --- > > .../bindings/soc/spacemit/spacemit,k1-syscon.yaml | 30 +++++++++++++++++++++- > > 1 file changed, 29 insertions(+), 1 deletion(-) > > > > diff --git a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml > > index d3a7c93c3c54..b8fc6632a392 100644 > > --- a/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml > > +++ b/Documentation/devicetree/bindings/soc/spacemit/spacemit,k1-syscon.yaml > > @@ -31,14 +31,18 @@ properties: > > maxItems: 1 > > > > clocks: > > - maxItems: 4 > > + minItems: 4 > > + maxItems: 6 > > > > clock-names: > > + minItems: 4 > > items: > > - const: osc > > - const: vctcxo_1m > > - const: vctcxo_3m > > - const: vctcxo_24m > > + - const: edp0_pll_pxclk > > + - const: edp1_pll_pxclk > > > > "#clock-cells": > > const: 1 > > @@ -95,6 +99,30 @@ allOf: > > - clocks > > - clock-names > > - "#clock-cells" > > + # Only the K3 APMU exposes the two eDP/DP PHY PLL pixel clocks as extra > > + # inputs (parents of its eDP pixel-clock muxes); every other variant has > > + # the four base oscillator inputs only. > > + - if: > > + properties: > > + compatible: > > + contains: > > + const: spacemit,k3-syscon-apmu > > + then: > > + properties: > > > + clocks: > > + minItems: 4 > > + maxItems: 6 > > + clock-names: > > + minItems: 4 > > + maxItems: 6 > > + else: > > + properties: > > + clocks: > > + minItems: 4 > > + maxItems: 4 > > + clock-names: > > + minItems: 4 > > + maxItems: 4 > > 4 is already the minimum, so it can be dropped on all of these. Thanks for the review. Will drop them in v2. Cody