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([2a01:e0a:c:37e0:8998:e0cf:68cc:1b62]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-426ce5e833dsm22538021f8f.53.2025.10.14.01.54.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 14 Oct 2025 01:54:26 -0700 (PDT) Message-ID: <34466c59-cea5-4a09-9dfa-83e25dbc49eb@redhat.com> Date: Tue, 14 Oct 2025 10:54:23 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] drm/ast: Blank with VGACR17 sync enable, always clear VGACRB6 sync off To: Thomas Zimmermann , airlied@redhat.com, dianders@chromium.org, nbowler@draconx.ca Cc: dri-devel@lists.freedesktop.org, stable@vger.kernel.org References: <20251014084743.18242-1-tzimmermann@suse.de> From: Jocelyn Falempe In-Reply-To: <20251014084743.18242-1-tzimmermann@suse.de> X-Mimecast-Spam-Score: 0 X-Mimecast-MFC-PROC-ID: pyki8P3h5szuwU8cDaX_NnNbf_yAeJG8mrGSR58i-zw_1760432067 X-Mimecast-Originator: redhat.com Content-Language: en-US, fr Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 14/10/2025 10:46, Thomas Zimmermann wrote: > Blank the display by disabling sync pulses with VGACR17<7>. Unblank > by reenabling them. This VGA setting should be supported by all Aspeed > hardware. > > Ast currently blanks via sync-off bits in VGACRB6. Not all BMCs handle > VGACRB6 correctly. After disabling sync during a reboot, some BMCs do > not reenable it after the soft reset. The display output remains dark. > When the display is off during boot, some BMCs set the sync-off bits in > VGACRB6, so the display remains dark. Observed with Blackbird AST2500 > BMCs. Clearing the sync-off bits unconditionally fixes these issues. > > Also do not modify VGASR1's SD bit for blanking, as it only disables GPU > access to video memory. Thanks, it looks good to me. Reviewed-by: Jocelyn Falempe > > v2: > - init vgacrb6 correctly (Jocelyn) > > Signed-off-by: Thomas Zimmermann > Fixes: ce3d99c83495 ("drm: Call drm_atomic_helper_shutdown() at shutdown time for misc drivers") > Tested-by: Nick Bowler > Reported-by: Nick Bowler > Closes: https://lore.kernel.org/dri-devel/wpwd7rit6t4mnu6kdqbtsnk5bhftgslio6e2jgkz6kgw6cuvvr@xbfswsczfqsi/ > Cc: Douglas Anderson > Cc: Dave Airlie > Cc: Thomas Zimmermann > Cc: Jocelyn Falempe > Cc: dri-devel@lists.freedesktop.org > Cc: # v6.7+ > --- > drivers/gpu/drm/ast/ast_mode.c | 18 ++++++++++-------- > drivers/gpu/drm/ast/ast_reg.h | 1 + > 2 files changed, 11 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/ast/ast_mode.c b/drivers/gpu/drm/ast/ast_mode.c > index 6b9d510c509d..9b6a7c54fbb5 100644 > --- a/drivers/gpu/drm/ast/ast_mode.c > +++ b/drivers/gpu/drm/ast/ast_mode.c > @@ -836,22 +836,24 @@ ast_crtc_helper_atomic_flush(struct drm_crtc *crtc, > static void ast_crtc_helper_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state) > { > struct ast_device *ast = to_ast_device(crtc->dev); > + u8 vgacr17 = 0x00; > + u8 vgacrb6 = 0xff; > > - ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xfc, 0x00); > - ast_set_index_reg_mask(ast, AST_IO_VGASRI, 0x01, 0xdf, 0x00); > + vgacr17 |= AST_IO_VGACR17_SYNC_ENABLE; > + vgacrb6 &= ~(AST_IO_VGACRB6_VSYNC_OFF | AST_IO_VGACRB6_HSYNC_OFF); > + > + ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x17, 0x7f, vgacr17); > + ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xfc, vgacrb6); > } > > static void ast_crtc_helper_atomic_disable(struct drm_crtc *crtc, struct drm_atomic_state *state) > { > struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); > struct ast_device *ast = to_ast_device(crtc->dev); > - u8 vgacrb6; > + u8 vgacr17 = 0xff; > > - ast_set_index_reg_mask(ast, AST_IO_VGASRI, 0x01, 0xdf, AST_IO_VGASR1_SD); > - > - vgacrb6 = AST_IO_VGACRB6_VSYNC_OFF | > - AST_IO_VGACRB6_HSYNC_OFF; > - ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xb6, 0xfc, vgacrb6); > + vgacr17 &= ~AST_IO_VGACR17_SYNC_ENABLE; > + ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0x17, 0x7f, vgacr17); > > /* > * HW cursors require the underlying primary plane and CRTC to > diff --git a/drivers/gpu/drm/ast/ast_reg.h b/drivers/gpu/drm/ast/ast_reg.h > index e15adaf3a80e..30578e3b07e4 100644 > --- a/drivers/gpu/drm/ast/ast_reg.h > +++ b/drivers/gpu/drm/ast/ast_reg.h > @@ -29,6 +29,7 @@ > #define AST_IO_VGAGRI (0x4E) > > #define AST_IO_VGACRI (0x54) > +#define AST_IO_VGACR17_SYNC_ENABLE BIT(7) /* called "Hardware reset" in docs */ > #define AST_IO_VGACR80_PASSWORD (0xa8) > #define AST_IO_VGACR99_VGAMEM_RSRV_MASK GENMASK(1, 0) > #define AST_IO_VGACRA1_VGAIO_DISABLED BIT(1)