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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5db736428e3sm437703a12.14.2025.01.16.13.16.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 16 Jan 2025 13:16:28 -0800 (PST) Message-ID: <404e8b7d-30ef-47f2-8a44-927b201d60ec@oss.qualcomm.com> Date: Thu, 16 Jan 2025 22:16:25 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH RFC 1/4] drm/msm/adreno: Add speedbin support for X1-85 To: Dmitry Baryshkov , Akhil P Oommen Cc: Konrad Dybcio , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Marijn Suijten , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Srinivas Kandagatla , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20250109-x1e-speedbin-b4-v1-0-009e812b7f2a@quicinc.com> <20250109-x1e-speedbin-b4-v1-1-009e812b7f2a@quicinc.com> <356986fa-e66c-4e78-ab92-2593b037ab9a@oss.qualcomm.com> <837602a7-bbd5-4436-ab9f-2b101bdcaac2@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: -sy_p4lRlfICjQ0S1_-b1NJSdyBbDdut X-Proofpoint-GUID: -sy_p4lRlfICjQ0S1_-b1NJSdyBbDdut X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-16_09,2025-01-16_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 impostorscore=0 mlxscore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 suspectscore=0 spamscore=0 malwarescore=0 bulkscore=0 clxscore=1015 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501160157 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 15.01.2025 8:59 PM, Dmitry Baryshkov wrote: > On Thu, Jan 16, 2025 at 01:07:17AM +0530, Akhil P Oommen wrote: >> On 1/9/2025 7:27 PM, Konrad Dybcio wrote: >>> On 8.01.2025 11:42 PM, Akhil P Oommen wrote: >>>> Adreno X1-85 has an additional bit which is at a non-contiguous >>>> location in qfprom. Add support for this new "hi" bit along with >>>> the speedbin mappings. >>>> --- >>>> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 5 +++++ >>>> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 15 ++++++++++++++- >>>> 2 files changed, 19 insertions(+), 1 deletion(-) >>>> >>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>> index 0c560e84ad5a53bb4e8a49ba4e153ce9cf33f7ae..e2261f50aabc6a2f931d810f3637dfdba5695f43 100644 >>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >>>> @@ -1412,6 +1412,11 @@ static const struct adreno_info a7xx_gpus[] = { >>>> .gmu_cgc_mode = 0x00020202, >>>> }, >>>> .address_space_size = SZ_256G, >>>> + .speedbins = ADRENO_SPEEDBINS( >>>> + { 0, 0 }, >>>> + { 263, 1 }, >>>> + { 315, 0 }, >>>> + ), >>>> .preempt_record_size = 4192 * SZ_1K, >>>> }, { >>>> .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ >>>> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c >>>> index 75f5367e73caace4648491b041f80b7c4d26bf89..7b31379eff444cf3f8ed0dcfd23c14920c13ee9d 100644 >>>> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c >>>> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c >>>> @@ -1078,7 +1078,20 @@ void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem) >>>> >>>> int adreno_read_speedbin(struct device *dev, u32 *speedbin) >>>> { >>>> - return nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); >>>> + u32 hi_bits = 0; >>>> + int ret; >>>> + >>>> + ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin", speedbin); >>>> + if (ret) >>>> + return ret; >>>> + >>>> + /* Some chipsets have MSB bits (BIT(8) and above) at a non-contiguous location */ >>>> + ret = nvmem_cell_read_variable_le_u32(dev, "speed_bin_hi", &hi_bits); >>>> + if (ret != -ENOENT) >>>> + return ret; >>>> + >>>> + *speedbin |= (hi_bits << 8); >>> >>> Now that we're overwriting speedbin, we should probably have some checks in >>> order to make sure somebody passing a too-wide cell to one of these won't >>> result in cripplingly-untraceable value corruption >>> >>> I guess we could just introduce nvmem_cell_read_variable_le_u8() and call it >>> a day? >> >> X1E is an outlier here, because this was fixed from the next chipset >> onward. For newer chipsets, we can use just the "speed_bin" node, which >> represents a contiguous 9 bits. So, just do a "WARN_ON(fls(speedbin) > >> 8)" here? > > Or extend nvmem core to support non-contiguous fields. This sounds more desirable, as we surely aren't the only ones with such a "feature".. Konrad