From: Stefan Agner <stefan@agner.ch>
To: Meng Yi <meng.yi@nxp.com>
Cc: dri-devel@lists.freedesktop.org
Subject: RE: [PATCH v2] drm/fsl-dcu: Fix endian issue when using clk_register_divider
Date: Fri, 02 Sep 2016 10:56:18 -0700 [thread overview]
Message-ID: <45432ec954ff7890a7b7cac13b86a2d2@agner.ch> (raw)
In-Reply-To: <DB6PR0401MB2631C47277DA0A69E2945364ECE20@DB6PR0401MB2631.eurprd04.prod.outlook.com>
On 2016-08-31 23:42, Meng Yi wrote:
> Hi Stefan,
>
> Could you test this patch on vf610, I think it will woks fine.
See comment below.
>
> When could you merge this path? And how about the patches for gamma
> correction and multi-layer support by the way?
Still need to look in those patches. I also have multi-layer patches in
our 4.4 tree:
http://git.toradex.com/cgit/linux-toradex.git/log/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_plane.c?h=toradex_vf_4.4-next
This changes also use one plane as cursor plane which probably makes
sense given that we have that many planes. I try to send out an
updated/rebased patchset soon.
>
> Best Regards,
> Meng
>
>> > > diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
>> > > b/drivers/gpu/drm/fsl- dcu/fsl_dcu_drm_drv.c index 7882387..a590ce8
>> > > 100644
>> > > --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
>> > > +++ b/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
>> > > @@ -386,7 +386,8 @@ static int fsl_dcu_drm_probe(struct
>> > > platform_device
>> > > *pdev)
>> > > snprintf(pix_clk_name, sizeof(pix_clk_name), "%s_pix",
>> > > pix_clk_in_name);
>> > > fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name,
>> > > pix_clk_in_name, 0, base + DCU_DIV_RATIO,
>> > > - 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
>> > > + !strcmp(fsl_dev->soc->name, "ls1021a")?24:0, 8,
>> > > + CLK_DIVIDER_ROUND_CLOSEST, NULL);
I don't like to sprinkle SoC detection all over the code, it makes it
harder when new SoC's with DCU appear. I will send out a patch making
use of struct fsl_dcu_soc_data or the like.
--
Stefan
>> >
>> > Tested-by: Meng Yi <meng.yi@nxp.com>
>>
>> On LS1021A-TWR board.
>> >
>> > > if (IS_ERR(fsl_dev->pix_clk)) {
>> > > dev_err(dev, "failed to register pix clk\n");
>> > > ret = PTR_ERR(fsl_dev->pix_clk);
>> > > --
>> > > 2.1.0.27.g96db324
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prev parent reply other threads:[~2016-09-02 18:01 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-08-26 9:53 [PATCH v2] drm/fsl-dcu: Fix endian issue when using clk_register_divider Meng Yi
2016-08-30 2:33 ` Meng Yi
2016-08-30 2:35 ` Meng Yi
2016-09-01 6:42 ` Meng Yi
2016-09-02 17:56 ` Stefan Agner [this message]
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