From mboxrd@z Thu Jan 1 00:00:00 1970 From: Steven Newbury Subject: Re: PCI resources above 4GB Date: Sun, 15 Apr 2012 11:19:52 +0100 Message-ID: <4F8AA0C8.7020001@snewbury.org.uk> References: <1333968563.5678.19.camel@infinity> <4F8467AA.90305@snewbury.org.uk> <4F848357.3060007@snewbury.org.uk> <4F848E10.1090703@snewbury.org.uk> <1334089568.4083.2.camel@Nokia-N900> <4F84A3EC.6030903@snewbury.org.uk> <1334229754.30606.7.camel@Nokia-N900> <1334248841.2910.6.camel@Nokia-N900> <4F89B5E8.3040906@snewbury.org.uk> <4F89BC84.50308@snewbury.org.uk> <4F89C513.3000006@sn ewbury.org.uk> <4F89CB16.2000908@snewbury.org.uk> <4F89CE43.7040200@snewbury.org.uk> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: Sender: linux-pci-owner@vger.kernel.org To: Yinghai Lu Cc: "Barnes, Jesse" , Dave Airlie , Bjorn Helgaas , linux-pci@vger.kernel.org, DRI mailing list List-Id: dri-devel@lists.freedesktop.org -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 On 14/04/12 21:48, Yinghai Lu wrote: > On Sat, Apr 14, 2012 at 12:21 PM, Steven Newbury > wrote: >> -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 >> >> On 14/04/12 20:08, Steven Newbury wrote: >>> On 14/04/12 19:42, Steven Newbury wrote: >>>> On 14/04/12 19:05, Steven Newbury wrote: >>>>> On 14/04/12 18:37, Steven Newbury wrote: >>>>>> On 12/04/12 17:40, Steven Newbury wrote: >>>>>>> On Thu, 12 Apr 2012, 17:07:33 BST, Yinghai Lu >>>>>>> wrote: >>> >>>>>>>> On Thu, Apr 12, 2012 at 4:22 AM, Steven Newbury >>>>>>>> wrote: >>>>>>>>> Thanks, that fixed it! :) I had a similar patch >>>>>>>>> I've been working on but I had my fix in the wrong >>>>>>>>> place! >>>>>>>>> >>>>>>>>> In the working case, initially the BIOS has set GMA >>>>>>>>> to within the low system DRAM 0xC0000000 obviously >>>>>>>>> invalid. This conflict is detected and it's >>>>>>>>> relallocated to 0x12000000. >>>>>>>>> >>>>>>>>> I've attempted to modify probe.c to disable 64-bit >>>>>>>>> BARs not allocated above 4G so they get >>>>>>>>> reallocated above when possible later. It seemed >>>>>>>>> to work, but again broke GMA despite the BAR >>>>>>>>> originally containing an invalid address as >>>>>>>>> mentioned above, it seems for some reason something >>>>>>>>> is different when the conflict is detected and >>>>>>>>> rellocated, compared to disabling it early then >>>>>>>>> allocating a valid value..? >>>>>>>>> >>>>>> I've created a new quirk utilising an extra PCI resource >>>>>> flag to force reallocation of the resource. It's the >>>>>> first approach I've had any success at. It does work. >>>>>> Only "Intel Page Flush" now gets allocated @0xe0000000! >>> >>> >>>>> Hopefully this should fix "Intel Flush Page" >>>> Need to export pci_bus_alloc_resource_fit for intel-gtt. >>> Nearly worked... Or at least it should have worked, but for >>> some reason the allocator failed to utilise >>> 0xe0000000-0xefffffff for 04:00.0 BAR0..? >>> >>> >>> pci 0000:03:08.0: BAR 15: can't assign mem pref (size >>> 0x18000000) >> Ah! Not enough space for the bridge window!:( >> > > please append pci=norom ... > That worked. Except of course the radeon driver can't POST the card without the ROM! ;) -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.19 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/ iEYEARECAAYFAk+KoMgACgkQGcb56gMuC62ZrACfcMJDlIVy8EfpwQyyAL91OH/d uEIAoMK2L1LEmy8OZIvaGRqt7UjxlYRM =v+/Q -----END PGP SIGNATURE-----