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From: "Hogander, Jouni" <jouni.hogander@intel.com>
To: "maarten.lankhorst@linux.intel.com"
	<maarten.lankhorst@linux.intel.com>,
	"airlied@gmail.com" <airlied@gmail.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"simona@ffwll.ch" <simona@ffwll.ch>
Cc: "intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>,
	"dri-devel@lists.freedesktop.org"
	<dri-devel@lists.freedesktop.org>
Subject: Re: [PATCH v4 00/12] Panel Replay + Adaptive sync
Date: Thu, 22 May 2025 05:25:19 +0000	[thread overview]
Message-ID: <4ba5f8375dea2ee73b430730abd11cd45fd12fcc.camel@intel.com> (raw)
In-Reply-To: <20250521115319.2380655-1-jouni.hogander@intel.com>

Hello DRM Maintainers,

I have two patches (01/12 and 02/12) in this set I would like to merge
via drm-intel/drm-intel-next. Is that ok to you? They are touching i915
display driver and drm_dp.h header and rest of the patch set is
depending on those changes. Can one of you ack those two patches?

Thank You in Advance,

Jouni Högander

On Wed, 2025-05-21 at 14:53 +0300, Jouni Högander wrote:
> This patch set is adding missing configuration to have Panel Replay
> and Adaptive Sync enabled simultaneously. Also some issues identified
> while debugging are fixed:
> 
> 1. Source PORT ALPM configuration has to made during modeset.
> 2. PHY_CMN1_CONTROL is not written according to HAS document
> 3. Wrong register field definitions for PORT_ALPM_LFPS_CTL.
> 
> Patches are tested on LunarLake and PantherLake using our reference
> panel supporting
> Adaptive Sync and Panel Replay.
> 
> v4:
>   - added DP_DSC_DECODE_CAPABILITY definitions
>   - use defined shift instead of hardcoded value
> v3:
>   - comment about DP2.1 corrected as DP2.1a
>   - referring patch removed from commit message
> v2:
>   - rework Panel Replay DPCD register definitions
>   - do not use hardcoded indices while accessing intel_dp->pr_dpcd
>   - ensure ALPM registers are not written on platform where they do
>     not exist
>   - remove kerneldoc comments
> 
> Jouni Högander (12):
>   drm/panelreplay: Panel Replay capability DPCD register definitions
>   drm/dp: Add Panel Replay capability bits from DP2.1 specification
>   drm/i915/psr: Read all Panel Replay capability registers from DPCD
>   drm/i915/alpm: Add PR_ALPM_CTL register definitions
>   drm/i915/alpm: Write PR_ALPM_CTL register
>   drm/i915/psr: Add interface to check if AUXLess ALPM is needed by
> PSR
>   drm/i915/alpm: Add new interface to check if AUXLess ALPM is used
>   drm/i915/alpm: Move port alpm configuration
>   drm/i915/display: Add PHY_CMN1_CONTROL register definitions
>   drm/i915/display: Add function to configure LFPS sending
>   drm/i915/psr: Fix using wrong mask in REG_FIELD_PREP
>   drm/i915/psr: Do not disable Panel Replay in case VRR is enabled
> 
>  drivers/gpu/drm/i915/display/intel_alpm.c     | 72 +++++++++++++----
> --
>  drivers/gpu/drm/i915/display/intel_alpm.h     |  4 ++
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c  | 32 +++++++++
>  drivers/gpu/drm/i915/display/intel_cx0_phy.h  |  2 +
>  .../gpu/drm/i915/display/intel_cx0_phy_regs.h |  3 +
>  drivers/gpu/drm/i915/display/intel_ddi.c      | 12 ++++
>  .../drm/i915/display/intel_display_types.h    |  4 +-
>  drivers/gpu/drm/i915/display/intel_psr.c      | 44 +++++++-----
>  drivers/gpu/drm/i915/display/intel_psr.h      |  2 +
>  drivers/gpu/drm/i915/display/intel_psr_regs.h | 14 +++-
>  include/drm/display/drm_dp.h                  | 24 +++++--
>  11 files changed, 168 insertions(+), 45 deletions(-)
> 


  parent reply	other threads:[~2025-05-22  5:25 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-05-21 11:53 [PATCH v4 00/12] Panel Replay + Adaptive sync Jouni Högander
2025-05-21 11:53 ` [PATCH v4 01/12] drm/panelreplay: Panel Replay capability DPCD register definitions Jouni Högander
2025-05-21 11:53 ` [PATCH v4 02/12] drm/dp: Add Panel Replay capability bits from DP2.1 specification Jouni Högander
2025-05-21 12:16   ` Nautiyal, Ankit K
2025-05-21 11:53 ` [PATCH v4 03/12] drm/i915/psr: Read all Panel Replay capability registers from DPCD Jouni Högander
2025-05-21 11:53 ` [PATCH v4 04/12] drm/i915/alpm: Add PR_ALPM_CTL register definitions Jouni Högander
2025-05-21 11:53 ` [PATCH v4 05/12] drm/i915/alpm: Write PR_ALPM_CTL register Jouni Högander
2025-05-21 11:53 ` [PATCH v4 06/12] drm/i915/psr: Add interface to check if AUXLess ALPM is needed by PSR Jouni Högander
2025-05-21 11:53 ` [PATCH v4 07/12] drm/i915/alpm: Add new interface to check if AUXLess ALPM is used Jouni Högander
2025-05-21 11:53 ` [PATCH v4 08/12] drm/i915/alpm: Move port alpm configuration Jouni Högander
2025-05-21 11:53 ` [PATCH v4 09/12] drm/i915/display: Add PHY_CMN1_CONTROL register definitions Jouni Högander
2025-05-21 11:53 ` [PATCH v4 10/12] drm/i915/display: Add function to configure LFPS sending Jouni Högander
2025-05-21 11:53 ` [PATCH v4 11/12] drm/i915/psr: Fix using wrong mask in REG_FIELD_PREP Jouni Högander
2025-05-21 11:53 ` [PATCH v4 12/12] drm/i915/psr: Do not disable Panel Replay in case VRR is enabled Jouni Högander
2025-05-22  5:25 ` Hogander, Jouni [this message]
2025-05-26 11:43   ` [PATCH v4 00/12] Panel Replay + Adaptive sync Maarten Lankhorst
2025-05-29  5:33     ` Hogander, Jouni

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