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amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: a59f9ea2-2867-4857-9e1b-08de9ee10291 X-MS-Exchange-CrossTenant-AuthSource: IA1PR12MB6435.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Apr 2026 13:30:38.3625 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: VP5WJKt/OglnyPxAwhHBB0jouzHh3YO0ut4aoS9yRyGN/aEDshsIZDx29NjnIQjk7+GdGGZqBckEecRigLH/aA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CYYPR12MB8962 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 4/20/2026 8:15 PM, Christian König wrote: > > > On 4/20/26 14:07, Honglei Huang wrote: >> From: Honglei Huang >> >> Add amdgpu drm SVM API definitions built on the >> DRM GPUSVM framework. >> >> This includes: >> - DRM_AMDGPU_GEM_SVM ioctl >> - AMDGPU_SVM_FLAG_* flags >> - AMDGPU_SVM_OP_SET_ATTR / AMDGPU_SVM_OP_GET_ATTR operations >> - AMDGPU_SVM_ATTR_* attribute types >> - AMDGPU_SVM_LOCATION_SYSMEM / AMDGPU_SVM_LOCATION_UNDEFINED >> - struct drm_amdgpu_svm_attribute and struct drm_amdgpu_gem_svm >> >> Signed-off-by: Honglei Huang >> --- >> include/uapi/drm/amdgpu_drm.h | 39 +++++++++++++++++++++++++++++++++++ >> 1 file changed, 39 insertions(+) >> >> diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h >> index 406a42be4..bed71ed9b 100644 >> --- a/include/uapi/drm/amdgpu_drm.h >> +++ b/include/uapi/drm/amdgpu_drm.h >> @@ -58,6 +58,7 @@ extern "C" { >> #define DRM_AMDGPU_USERQ_SIGNAL 0x17 >> #define DRM_AMDGPU_USERQ_WAIT 0x18 >> #define DRM_AMDGPU_GEM_LIST_HANDLES 0x19 >> +#define DRM_AMDGPU_GEM_SVM 0x1a >> >> #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) >> #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) >> @@ -79,6 +80,7 @@ extern "C" { >> #define DRM_IOCTL_AMDGPU_USERQ_SIGNAL DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_SIGNAL, struct drm_amdgpu_userq_signal) >> #define DRM_IOCTL_AMDGPU_USERQ_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_USERQ_WAIT, struct drm_amdgpu_userq_wait) >> #define DRM_IOCTL_AMDGPU_GEM_LIST_HANDLES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_LIST_HANDLES, struct drm_amdgpu_gem_list_handles) >> +#define DRM_IOCTL_AMDGPU_GEM_SVM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_SVM, struct drm_amdgpu_gem_svm) >> >> /** >> * DOC: memory domains >> @@ -1665,6 +1667,43 @@ struct drm_color_ctm_3x4 { >> __u64 matrix[12]; >> }; >> >> +#define AMDGPU_SVM_FLAG_HOST_ACCESS 0x00000001 >> +#define AMDGPU_SVM_FLAG_COHERENT 0x00000002 >> +#define AMDGPU_SVM_FLAG_HIVE_LOCAL 0x00000004 >> +#define AMDGPU_SVM_FLAG_GPU_RO 0x00000008 >> +#define AMDGPU_SVM_FLAG_GPU_EXEC 0x00000010 >> +#define AMDGPU_SVM_FLAG_GPU_READ_MOSTLY 0x00000020 >> +#define AMDGPU_SVM_FLAG_GPU_ALWAYS_MAPPED 0x00000040 >> +#define AMDGPU_SVM_FLAG_EXT_COHERENT 0x00000080 >> + >> +#define AMDGPU_SVM_OP_SET_ATTR 0 >> +#define AMDGPU_SVM_OP_GET_ATTR 1 >> + >> +#define AMDGPU_SVM_ATTR_PREFERRED_LOC 0 >> +#define AMDGPU_SVM_ATTR_PREFETCH_LOC 1 > > Up till here the interface makes perfect sense, but then it becomes a bit fuzzy. > >> +#define AMDGPU_SVM_ATTR_ACCESS 2 >> +#define AMDGPU_SVM_ATTR_ACCESS_IN_PLACE 3 >> +#define AMDGPU_SVM_ATTR_NO_ACCESS 4 > > Why are those separate attributes? What is the difference between those? Really thanks for the comments, I have some content mistaken in V2, so I updated the V3 to fix that. For the header they are same. for other content please review the V3, sorry about that. And will fix the concern you raised in next version. So the meaning of AMDGPU_SVM_ATTR_ACCESS and AMDGPU_SVM_ATTR_NO_ACCESS are clear, GPU can access it or not, and the SVM can set the preferred location, it can be in VRAM or system, for AMDGPU_SVM_ATTR_ACCESS it can be migrated between RAM and VRAM. For AMDGPU_SVM_ATTR_ACCESS_IN_PLACE, it can not migrate, GPU only can access it in the initial place. > >> +#define AMDGPU_SVM_ATTR_SET_FLAGS 5 >> +#define AMDGPU_SVM_ATTR_CLR_FLAGS 6 > > Why is that separated into set and clear flags? This method inherits from KFD and is also designed to be compatible with upper layer applications such as ROCR. > >> +#define AMDGPU_SVM_ATTR_GRANULARITY 7 >> + >> +#define AMDGPU_SVM_LOCATION_SYSMEM 0 >> +#define AMDGPU_SVM_LOCATION_UNDEFINED 0xffffffff > > No location for device local memory? Vaule > 0 means for device memory, in xe_svm, it seems like it uses fd for device local memory. > >> + >> +struct drm_amdgpu_svm_attribute { >> + __u32 type; >> + __u32 value; >> +}; >> + >> +struct drm_amdgpu_gem_svm { >> + __u64 start_addr; >> + __u64 size; >> + __u32 operation; >> + __u32 nattr; >> + __u64 attrs_ptr; >> +}; > > Those struct make perfect sense but clearly need documentation. Preferable as kerneldoc. > > And we usually use unions in this header to separate the input from the output parameters. Got it will add documentation for it and will use unions in next version. Really thanks for the comments. Regards, Honglei > > Regards, > Christian. > >> + >> #if defined(__cplusplus) >> } >> #endif >