From: Maarten Lankhorst <maarten.lankhorst@canonical.com>
To: Dan Carpenter <dan.carpenter@oracle.com>
Cc: David Airlie <airlied@linux.ie>,
kernel-janitors@vger.kernel.org, Ben Skeggs <bskeggs@redhat.com>,
dri-devel@lists.freedesktop.org
Subject: Re: [patch] drm/nvc0-/gr: shift wrapping bug in nvc0_grctx_generate_r406800()
Date: Fri, 12 Jul 2013 09:54:57 +0200 [thread overview]
Message-ID: <51DFB651.9020008@canonical.com> (raw)
In-Reply-To: <20130712063329.GA29320@longonot.mountain>
Op 12-07-13 08:33, Dan Carpenter schreef:
> We care about the upper 32 bits here so we have to use 1ULL instead of 1
> to avoid a shift wrapping bug.
>
> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
>
> diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
> index 64dca26..fe67415 100644
> --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
> +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
> @@ -1039,7 +1039,7 @@ nvc0_grctx_generate_r406800(struct nvc0_graph_priv *priv)
> } while (!tpcnr[gpc]);
> tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
>
> - tpc_set |= 1 << ((gpc * 8) + tpc);
> + tpc_set |= 1ULL << ((gpc * 8) + tpc);
> }
>
> nv_wr32(priv, 0x406800 + (i * 0x20), lower_32_bits(tpc_set));
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Any other code in nouveau that looks bugged?
prev parent reply other threads:[~2013-07-12 7:54 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-07-12 6:33 [patch] drm/nvc0-/gr: shift wrapping bug in nvc0_grctx_generate_r406800() Dan Carpenter
2013-07-12 7:54 ` Maarten Lankhorst [this message]
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