* [patch] drm/nvc0-/gr: shift wrapping bug in nvc0_grctx_generate_r406800()
@ 2013-07-12 6:33 Dan Carpenter
2013-07-12 7:54 ` Maarten Lankhorst
0 siblings, 1 reply; 2+ messages in thread
From: Dan Carpenter @ 2013-07-12 6:33 UTC (permalink / raw)
To: David Airlie; +Cc: Ben Skeggs, dri-devel, kernel-janitors
We care about the upper 32 bits here so we have to use 1ULL instead of 1
to avoid a shift wrapping bug.
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
index 64dca26..fe67415 100644
--- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
+++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
@@ -1039,7 +1039,7 @@ nvc0_grctx_generate_r406800(struct nvc0_graph_priv *priv)
} while (!tpcnr[gpc]);
tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
- tpc_set |= 1 << ((gpc * 8) + tpc);
+ tpc_set |= 1ULL << ((gpc * 8) + tpc);
}
nv_wr32(priv, 0x406800 + (i * 0x20), lower_32_bits(tpc_set));
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [patch] drm/nvc0-/gr: shift wrapping bug in nvc0_grctx_generate_r406800()
2013-07-12 6:33 [patch] drm/nvc0-/gr: shift wrapping bug in nvc0_grctx_generate_r406800() Dan Carpenter
@ 2013-07-12 7:54 ` Maarten Lankhorst
0 siblings, 0 replies; 2+ messages in thread
From: Maarten Lankhorst @ 2013-07-12 7:54 UTC (permalink / raw)
To: Dan Carpenter; +Cc: David Airlie, kernel-janitors, Ben Skeggs, dri-devel
Op 12-07-13 08:33, Dan Carpenter schreef:
> We care about the upper 32 bits here so we have to use 1ULL instead of 1
> to avoid a shift wrapping bug.
>
> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
>
> diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
> index 64dca26..fe67415 100644
> --- a/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
> +++ b/drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
> @@ -1039,7 +1039,7 @@ nvc0_grctx_generate_r406800(struct nvc0_graph_priv *priv)
> } while (!tpcnr[gpc]);
> tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
>
> - tpc_set |= 1 << ((gpc * 8) + tpc);
> + tpc_set |= 1ULL << ((gpc * 8) + tpc);
> }
>
> nv_wr32(priv, 0x406800 + (i * 0x20), lower_32_bits(tpc_set));
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Any other code in nouveau that looks bugged?
^ permalink raw reply [flat|nested] 2+ messages in thread
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