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* Radeon drivers on PowerPC (e500)
@ 2014-06-17 19:14 Martyn Welch
  2014-06-18  1:05 ` Dave Airlie
  0 siblings, 1 reply; 6+ messages in thread
From: Martyn Welch @ 2014-06-17 19:14 UTC (permalink / raw)
  To: David Airlie, Alex Deucher, Christian König; +Cc: dri-devel

Hi,

I've been asked to try and get a r600 based (E6460) graphics card 
running on a machine powered by a Freescale p4080 (e500 core). I've run 
into a bit of a problem.

I have the driver built into the kernel at this point. When I boot the 
card is detected and it seems to be finding the fimware (I'm also 
building in the required firmware blobs), but I get the following messages:

[drm] Initialized drm 1.1.0 20060810
[drm] radeon defaulting to kernel modesetting.
[drm] radeon kernel modesetting enabled.
[drm] initializing kernel modesetting (CAICOS 0x1002:0x6763 0x1775:0xC6A7).
[drm] register mmio base: 0x10000000
[drm] register mmio size: 131072
ATOM BIOS: GE
[drm] GPU not posted. posting now...
radeon 0000:04:00.0: VRAM: 512M 0x0000000000000000 - 0x000000001FFFFFFF 
(512M used)
radeon 0000:04:00.0: GTT: 512M 0x0000000020000000 - 0x000000003FFFFFFF
[drm] Detected VRAM RAM=512M, BAR=256M
[drm] RAM width 64bits DDR
[TTM] Zone  kernel: Available graphics memory: 338754 kiB
[TTM] Zone highmem: Available graphics memory: 994110 kiB
[TTM] Initializing pool allocator
[TTM] Initializing DMA pool allocator
[drm] radeon: 512M of VRAM memory ready
[drm] radeon: 512M of GTT memory ready.
[drm] Supports vblank timestamp caching Rev 1 (10.10.2010).
[drm] Driver supports precise vblank timestamp query.
radeon 0000:04:00.0: radeon: using MSI.
[drm] radeon: irq initialized.
[drm] GART: num cpu pages 131072, num gpu pages 131072
[drm] probing gen 2 caps for device 111d:808a = 2/0
[drm] enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0
[drm] Loading CAICOS Microcode
__ioremap_caller(140000, 4096, 4194304, c02eab20)__ioremap(): phys addr 
0x140000 is RAM lr ttm_bo_kmap
radeon 0000:04:00.0: disabling GPU acceleration
radeon 0000:04:00.0: e957e400 unpin not necessary
radeon 0000:04:00.0: e957e400 unpin not necessary
[drm] Radeon Display Connectors
[drm] Connector 0:
[drm]   DP-1
[drm]   HPD2
[drm]   HPD3
[drm]   DDC: 0x6450 0x6450 0x6454 0x6454 0x6458 0x6458 0x645c 0x645c
[drm]   Encoders:
[drm]     DFP2: INTERNAL_UNIPHY1
[drm] Connector 2:
[drm]   DVI-I-1
[drm]   HPD1
[drm]   DDC: 0x6430 0x6430 0x6434 0x6434 0x6438 0x6438 0x643c 0x643c
[drm]   Encoders:
[drm]     DFP3: INTERNAL_UNIPHY
[drm]     CRT1: INTERNAL_KLDSCP_DAC1
[drm] Internal thermal controller with fan control
[drm] radeon: power management initialized
__ioremap_caller(141000, 5242880, 4194304, c02eab20)__ioremap(): phys 
addr 0x141000 is RAM lr ttm_bo_kmap
[drm:radeonfb_create] *ERROR* failed to create fbcon object -12
[drm] Initialized radeon 2.29.0 20080528 for 0000:04:00.0 on minor 0

There are failed attempts to ioremap RAM, initially as part of 
r600_vram_scratch_init() and again I guess mapping the GART?

On the e500, overlapping TLBs are not allowed and there is an explict 
check in arch/powerpc/mm/pgtable_32.c __ioremap_caller() to protect 
against ioremapping RAM that's already got TLB entries which is 
resulting in the error messages.

I'm out of ideas, any pointers or suggestions on how I might get this 
working? Has this ever been attempted before?

Martyn

-- 
Martyn Welch (Lead Software Engineer)  | Registered in England and Wales
GE Intelligent Platforms               | (3828642) at 100 Barbirolli Square
T +44(0)1327322748                     | Manchester, M2 3AB
E martyn.welch@ge.com                  | VAT:GB 927559189

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: Radeon drivers on PowerPC (e500)
  2014-06-17 19:14 Radeon drivers on PowerPC (e500) Martyn Welch
@ 2014-06-18  1:05 ` Dave Airlie
  2014-06-18  1:48   ` Benjamin Herrenschmidt
  2014-06-18  8:09   ` Martyn Welch
  0 siblings, 2 replies; 6+ messages in thread
From: Dave Airlie @ 2014-06-18  1:05 UTC (permalink / raw)
  To: Martyn Welch; +Cc: Alex Deucher, Christian König, dri-devel

On 18 June 2014 05:14, Martyn Welch <martyn.welch@ge.com> wrote:
> Hi,
>
> I've been asked to try and get a r600 based (E6460) graphics card running on
> a machine powered by a Freescale p4080 (e500 core). I've run into a bit of a
> problem.
>
> I have the driver built into the kernel at this point. When I boot the card
> is detected and it seems to be finding the fimware (I'm also building in the
> required firmware blobs), but I get the following messages:
>
> [drm] Initialized drm 1.1.0 20060810
> [drm] radeon defaulting to kernel modesetting.
> [drm] radeon kernel modesetting enabled.
> [drm] initializing kernel modesetting (CAICOS 0x1002:0x6763 0x1775:0xC6A7).
> [drm] register mmio base: 0x10000000
> [drm] register mmio size: 131072
> ATOM BIOS: GE
> [drm] GPU not posted. posting now...
> radeon 0000:04:00.0: VRAM: 512M 0x0000000000000000 - 0x000000001FFFFFFF
> (512M used)
> radeon 0000:04:00.0: GTT: 512M 0x0000000020000000 - 0x000000003FFFFFFF
> [drm] Detected VRAM RAM=512M, BAR=256M
> [drm] RAM width 64bits DDR
> [TTM] Zone  kernel: Available graphics memory: 338754 kiB
> [TTM] Zone highmem: Available graphics memory: 994110 kiB
> [TTM] Initializing pool allocator
> [TTM] Initializing DMA pool allocator
> [drm] radeon: 512M of VRAM memory ready
> [drm] radeon: 512M of GTT memory ready.
> [drm] Supports vblank timestamp caching Rev 1 (10.10.2010).
> [drm] Driver supports precise vblank timestamp query.
> radeon 0000:04:00.0: radeon: using MSI.
> [drm] radeon: irq initialized.
> [drm] GART: num cpu pages 131072, num gpu pages 131072
> [drm] probing gen 2 caps for device 111d:808a = 2/0
> [drm] enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0
> [drm] Loading CAICOS Microcode
> __ioremap_caller(140000, 4096, 4194304, c02eab20)__ioremap(): phys addr
> 0x140000 is RAM lr ttm_bo_kmap
> radeon 0000:04:00.0: disabling GPU acceleration
> radeon 0000:04:00.0: e957e400 unpin not necessary
> radeon 0000:04:00.0: e957e400 unpin not necessary
> [drm] Radeon Display Connectors
> [drm] Connector 0:
> [drm]   DP-1
> [drm]   HPD2
> [drm]   HPD3
> [drm]   DDC: 0x6450 0x6450 0x6454 0x6454 0x6458 0x6458 0x645c 0x645c
> [drm]   Encoders:
> [drm]     DFP2: INTERNAL_UNIPHY1
> [drm] Connector 2:
> [drm]   DVI-I-1
> [drm]   HPD1
> [drm]   DDC: 0x6430 0x6430 0x6434 0x6434 0x6438 0x6438 0x643c 0x643c
> [drm]   Encoders:
> [drm]     DFP3: INTERNAL_UNIPHY
> [drm]     CRT1: INTERNAL_KLDSCP_DAC1
> [drm] Internal thermal controller with fan control
> [drm] radeon: power management initialized
> __ioremap_caller(141000, 5242880, 4194304, c02eab20)__ioremap(): phys addr
> 0x141000 is RAM lr ttm_bo_kmap
> [drm:radeonfb_create] *ERROR* failed to create fbcon object -12
> [drm] Initialized radeon 2.29.0 20080528 for 0000:04:00.0 on minor 0
>
> There are failed attempts to ioremap RAM, initially as part of
> r600_vram_scratch_init() and again I guess mapping the GART?
>
> On the e500, overlapping TLBs are not allowed and there is an explict check
> in arch/powerpc/mm/pgtable_32.c __ioremap_caller() to protect against
> ioremapping RAM that's already got TLB entries which is resulting in the
> error messages.

I don't think we ever ioremap GART, it should kmap GART pages, ioremap
should only happen for VRAM areas AFAIK,

This isn't some 32-bit vs 36-bit BAR or something, I seem to remember BenH
mentioning something like that before.

Dave.

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: Radeon drivers on PowerPC (e500)
  2014-06-18  1:05 ` Dave Airlie
@ 2014-06-18  1:48   ` Benjamin Herrenschmidt
  2014-06-18  8:39     ` Martyn Welch
  2014-06-26  8:28     ` Martyn Welch
  2014-06-18  8:09   ` Martyn Welch
  1 sibling, 2 replies; 6+ messages in thread
From: Benjamin Herrenschmidt @ 2014-06-18  1:48 UTC (permalink / raw)
  To: Dave Airlie, Martyn Welch; +Cc: Alex Deucher, Christian König, dri-devel

On Wed, 2014-06-18 at 11:05 +1000, Dave Airlie wrote:
> 
> I don't think we ever ioremap GART, it should kmap GART pages, ioremap
> should only happen for VRAM areas AFAIK,
> 
> This isn't some 32-bit vs 36-bit BAR or something, I seem to remember BenH
> mentioning something like that before.

Yes, it's a recurring problem in the DRM with physical addresses that are
bigger than 32-bit on 32-bit systems. There have been patches done to
fix that but afaik never quite "completed". I can dig internally if
I can put my hand onto something.

If possible at all, can you try to configure your SoC to bring the MMIO
space of the PCIe within the bottom 32-bit of the chip address space ?

(Or use a 64-bit e5500 based chip ? :-)

Cheers,
Ben.

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: Radeon drivers on PowerPC (e500)
  2014-06-18  1:05 ` Dave Airlie
  2014-06-18  1:48   ` Benjamin Herrenschmidt
@ 2014-06-18  8:09   ` Martyn Welch
  1 sibling, 0 replies; 6+ messages in thread
From: Martyn Welch @ 2014-06-18  8:09 UTC (permalink / raw)
  To: Dave Airlie; +Cc: Alex Deucher, Christian König, dri-devel



On 18/06/14 02:05, Dave Airlie wrote:
> On 18 June 2014 05:14, Martyn Welch <martyn.welch@ge.com> wrote:
>> Hi,
>>
>> I've been asked to try and get a r600 based (E6460) graphics card running on
>> a machine powered by a Freescale p4080 (e500 core). I've run into a bit of a
>> problem.
>>
>> I have the driver built into the kernel at this point. When I boot the card
>> is detected and it seems to be finding the fimware (I'm also building in the
>> required firmware blobs), but I get the following messages:
>>
>> [drm] Initialized drm 1.1.0 20060810
>> [drm] radeon defaulting to kernel modesetting.
>> [drm] radeon kernel modesetting enabled.
>> [drm] initializing kernel modesetting (CAICOS 0x1002:0x6763 0x1775:0xC6A7).
>> [drm] register mmio base: 0x10000000
>> [drm] register mmio size: 131072
>> ATOM BIOS: GE
>> [drm] GPU not posted. posting now...
>> radeon 0000:04:00.0: VRAM: 512M 0x0000000000000000 - 0x000000001FFFFFFF
>> (512M used)
>> radeon 0000:04:00.0: GTT: 512M 0x0000000020000000 - 0x000000003FFFFFFF
>> [drm] Detected VRAM RAM=512M, BAR=256M
>> [drm] RAM width 64bits DDR
>> [TTM] Zone  kernel: Available graphics memory: 338754 kiB
>> [TTM] Zone highmem: Available graphics memory: 994110 kiB
>> [TTM] Initializing pool allocator
>> [TTM] Initializing DMA pool allocator
>> [drm] radeon: 512M of VRAM memory ready
>> [drm] radeon: 512M of GTT memory ready.
>> [drm] Supports vblank timestamp caching Rev 1 (10.10.2010).
>> [drm] Driver supports precise vblank timestamp query.
>> radeon 0000:04:00.0: radeon: using MSI.
>> [drm] radeon: irq initialized.
>> [drm] GART: num cpu pages 131072, num gpu pages 131072
>> [drm] probing gen 2 caps for device 111d:808a = 2/0
>> [drm] enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0
>> [drm] Loading CAICOS Microcode
>> __ioremap_caller(140000, 4096, 4194304, c02eab20)__ioremap(): phys addr
>> 0x140000 is RAM lr ttm_bo_kmap
>> radeon 0000:04:00.0: disabling GPU acceleration
>> radeon 0000:04:00.0: e957e400 unpin not necessary
>> radeon 0000:04:00.0: e957e400 unpin not necessary
>> [drm] Radeon Display Connectors
>> [drm] Connector 0:
>> [drm]   DP-1
>> [drm]   HPD2
>> [drm]   HPD3
>> [drm]   DDC: 0x6450 0x6450 0x6454 0x6454 0x6458 0x6458 0x645c 0x645c
>> [drm]   Encoders:
>> [drm]     DFP2: INTERNAL_UNIPHY1
>> [drm] Connector 2:
>> [drm]   DVI-I-1
>> [drm]   HPD1
>> [drm]   DDC: 0x6430 0x6430 0x6434 0x6434 0x6438 0x6438 0x643c 0x643c
>> [drm]   Encoders:
>> [drm]     DFP3: INTERNAL_UNIPHY
>> [drm]     CRT1: INTERNAL_KLDSCP_DAC1
>> [drm] Internal thermal controller with fan control
>> [drm] radeon: power management initialized
>> __ioremap_caller(141000, 5242880, 4194304, c02eab20)__ioremap(): phys addr
>> 0x141000 is RAM lr ttm_bo_kmap
>> [drm:radeonfb_create] *ERROR* failed to create fbcon object -12
>> [drm] Initialized radeon 2.29.0 20080528 for 0000:04:00.0 on minor 0
>>
>> There are failed attempts to ioremap RAM, initially as part of
>> r600_vram_scratch_init() and again I guess mapping the GART?
>>
>> On the e500, overlapping TLBs are not allowed and there is an explict check
>> in arch/powerpc/mm/pgtable_32.c __ioremap_caller() to protect against
>> ioremapping RAM that's already got TLB entries which is resulting in the
>> error messages.
>
> I don't think we ever ioremap GART, it should kmap GART pages, ioremap
> should only happen for VRAM areas AFAIK,
>

Ah, quite possibly, I hadn't looked in any depth further than the 
initial failure with r600_vram_scratch_init() as that was going to be a 
bit of a blocker.

> This isn't some 32-bit vs 36-bit BAR or something, I seem to remember BenH
> mentioning something like that before.
>

Thanks Dave.

Martyn

-- 
Martyn Welch (Lead Software Engineer)  | Registered in England and Wales
GE Intelligent Platforms               | (3828642) at 100 Barbirolli Square
T +44(0)1327322748                     | Manchester, M2 3AB
E martyn.welch@ge.com                  | VAT:GB 927559189

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: Radeon drivers on PowerPC (e500)
  2014-06-18  1:48   ` Benjamin Herrenschmidt
@ 2014-06-18  8:39     ` Martyn Welch
  2014-06-26  8:28     ` Martyn Welch
  1 sibling, 0 replies; 6+ messages in thread
From: Martyn Welch @ 2014-06-18  8:39 UTC (permalink / raw)
  To: Benjamin Herrenschmidt, Dave Airlie
  Cc: Alex Deucher, Christian König, dri-devel



On 18/06/14 02:48, Benjamin Herrenschmidt wrote:
> On Wed, 2014-06-18 at 11:05 +1000, Dave Airlie wrote:
>>
>> I don't think we ever ioremap GART, it should kmap GART pages, ioremap
>> should only happen for VRAM areas AFAIK,
>>
>> This isn't some 32-bit vs 36-bit BAR or something, I seem to remember BenH
>> mentioning something like that before.
>
> Yes, it's a recurring problem in the DRM with physical addresses that are
> bigger than 32-bit on 32-bit systems. There have been patches done to
> fix that but afaik never quite "completed". I can dig internally if
> I can put my hand onto something.
>

Thanks Ben, that would be much appreciated.

> If possible at all, can you try to configure your SoC to bring the MMIO
> space of the PCIe within the bottom 32-bit of the chip address space ?
>

Will give it a try.

Thanks again,

Martyn

-- 
Martyn Welch (Lead Software Engineer)  | Registered in England and Wales
GE Intelligent Platforms               | (3828642) at 100 Barbirolli Square
T +44(0)1327322748                     | Manchester, M2 3AB
E martyn.welch@ge.com                  | VAT:GB 927559189

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: Radeon drivers on PowerPC (e500)
  2014-06-18  1:48   ` Benjamin Herrenschmidt
  2014-06-18  8:39     ` Martyn Welch
@ 2014-06-26  8:28     ` Martyn Welch
  1 sibling, 0 replies; 6+ messages in thread
From: Martyn Welch @ 2014-06-26  8:28 UTC (permalink / raw)
  To: Benjamin Herrenschmidt, Dave Airlie
  Cc: Alex Deucher, Christian König, dri-devel


On 18/06/14 02:48, Benjamin Herrenschmidt wrote:
> On Wed, 2014-06-18 at 11:05 +1000, Dave Airlie wrote:
>>
>> I don't think we ever ioremap GART, it should kmap GART pages, ioremap
>> should only happen for VRAM areas AFAIK,
>>
>> This isn't some 32-bit vs 36-bit BAR or something, I seem to remember BenH
>> mentioning something like that before.
>
> Yes, it's a recurring problem in the DRM with physical addresses that are
> bigger than 32-bit on 32-bit systems. There have been patches done to
> fix that but afaik never quite "completed". I can dig internally if
> I can put my hand onto something.
>
> If possible at all, can you try to configure your SoC to bring the MMIO
> space of the PCIe within the bottom 32-bit of the chip address space ?
>

I've go a hold of a U-Boot build that brings the chip up in 32-bit mode 
and modified the DTS to suit. Seemed like the easiest way to see whether 
it would work. It does. I have a Radeon E6460 showing an X display, at 
the moment using the fbdev driver. Baby steps...

> (Or use a 64-bit e5500 based chip ? :-)
>

Yeah, haven't got any of those lying around ;-)

Thanks guys,

Martyn

-- 
Martyn Welch (Lead Software Engineer)  | Registered in England and Wales
GE Intelligent Platforms               | (3828642) at 100 Barbirolli Square
T +44(0)1327322748                     | Manchester, M2 3AB
E martyn.welch@ge.com                  | VAT:GB 927559189

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2014-06-26  8:28 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-06-17 19:14 Radeon drivers on PowerPC (e500) Martyn Welch
2014-06-18  1:05 ` Dave Airlie
2014-06-18  1:48   ` Benjamin Herrenschmidt
2014-06-18  8:39     ` Martyn Welch
2014-06-26  8:28     ` Martyn Welch
2014-06-18  8:09   ` Martyn Welch

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