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([2a02:810d:340:2e50:b4a9:f772:3340:fbf9]) by smtp.gmail.com with ESMTPSA id p5sm5580060wrg.49.2020.04.21.11.17.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 21 Apr 2020 11:17:48 -0700 (PDT) Subject: Re: [PATCH v6 00/12] ARM/MIPS: DTS: add child nodes describing the PVRSGX GPU present in some OMAP SoC and JZ4780 (and many more) To: Maxime Ripard References: <20200415101008.zxzxca2vlfsefpdv@gilmour.lan> <2E3401F1-A106-4396-8FE6-51CAB72926A4@goldelico.com> <20200415130233.rgn7xrtwqicptke2@gilmour.lan> <10969e64-fe1f-d692-4984-4ba916bd2161@gmail.com> <20200420073842.nx4xb3zqvu23arkc@gilmour.lan> <20200421112129.zjmkmzo3aftksgka@gilmour.lan> From: Philipp Rossak Message-ID: <5749af21-e707-c998-c83b-50c48867c9e8@gmail.com> Date: Tue, 21 Apr 2020 18:42:17 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: <20200421112129.zjmkmzo3aftksgka@gilmour.lan> Content-Language: en-US X-Mailman-Approved-At: Wed, 22 Apr 2020 06:54:41 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , David Airlie , "H. Nikolaus Schaller" , "open list:DRM PANEL DRIVERS" , linux-mips@vger.kernel.org, Paul Cercueil , linux-samsung-soc@vger.kernel.org, Discussions about the Letux Kernel , Paul Burton , Krzysztof Kozlowski , Tony Lindgren , Chen-Yu Tsai , Kukjin Kim , James Hogan , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , =?UTF-8?Q?Beno=c3=aet_Cousson?= , Rob Herring , linux-omap , arm-soc , Thomas Bogendoerfer , OpenPVRSGX Linux Driver Group , Linux Kernel Mailing List , Ralf Baechle , kernel@pyra-handheld.com Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi, On 21.04.20 13:21, Maxime Ripard wrote: > Hi, > > On Tue, Apr 21, 2020 at 11:57:33AM +0200, Philipp Rossak wrote: >> On 20.04.20 09:38, Maxime Ripard wrote: >>> Hi, >>> >>> On Fri, Apr 17, 2020 at 02:09:06PM +0200, Philipp Rossak wrote: >>>>>> I'm a bit skeptical on that one since it doesn't even list the >>>>>> interrupts connected to the GPU that the binding mandates. >>>>> >>>>> I think he left it out for a future update. >>>>> But best he comments himself. >>>> >>>> I'm currently working on those bindings. They are now 90% done, but they are >>>> not finished till now. Currently there is some mainline support missing to >>>> add the full binding. The A83T and also the A31/A31s have a GPU Power Off >>>> Gating Register in the R_PRCM module, that is not supported right now in >>>> Mainline. The Register need to be written when the GPU is powered on and >>>> off. >>>> >>>> @Maxime: I totally agree on your point that a demo needs to be provided >>>> before the related DTS patches should be provided. That's the reason why I >>>> added the gpu placeholder patches. >>>> Do you have an idea how a driver for the R_PRCM stuff can look like? I'm not >>>> that experienced with the clock driver framework. >>> >>> It looks like a power-domain to me, so you'd rather plug that into the genpd >>> framework. >> >> I had a look on genpd and I'm not really sure if that fits. >> >> It is basically some bit that verify that the clocks should be enabled or >> disabled. > > No, it can do much more than that. It's a framework to control the SoCs power > domains, so clocks might be a part of it, but most of the time it's going to be > about powering up a particular device. > So I think I've found now the right piece of documentation and a driver that implements something similar [1]. So I will write a similar driver like linked above that only sets the right bits for A83T and A31/A31s. Do you think this is the right approach? >> I think this is better placed somewhere in the clocking framework. >> I see there more similarities to the gating stuff. >> Do you think it is suitable to implement it like the clock gating? > > I'm really not sure what makes you think that this should be modelled as a > clock? > Looks like I looked in the wrong place and got some information that are not suitable for this. >>>> The big question is right now how to proceed with the A83T and A31s patches. >>>> I see there three options, which one do you prefer?: >>>> >>>> 1. Provide now placeholder patches and send new patches, if everything is >>>> clear and other things are mainlined >>>> 2. Provide now patches as complete as possible and provide later patches to >>>> complete them when the R_PRCM things are mainlined >>>> 3. Leave them out, till the related work is mainlined and the bindings are >>>> final. >>> >>> Like I said, the DT *has* to be backward-compatible, so for any DT patch that >>> you are asking to be merged, you should be prepared to support it indefinitely >>> and be able to run from it, and you won't be able to change the bindings later >>> on. >> >> I agree on your points. But is this also suitable to drivers that are >> currently off tree and might be merged in one or two years? > > This is what we done for the Mali. The devicetree binding was first done for the > out-of-tree driver, and then lima/panfrost reused it. > > The key thing here is to have enough confidence about how the hardware works so > that you can accurately describe it. Ok thanks! So I will resend my patches when the work got a more mature state and we know enough about the Hardware. Cheers, Philipp [1]: https://elixir.bootlin.com/linux/latest/source/drivers/soc/amlogic/meson-gx-pwrc-vpu.c _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel