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[76.244.6.13]) by smtp.gmail.com with ESMTPSA id r4-20020a056870414400b0017ae909afe8sm793608oad.34.2023.04.13.08.27.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Apr 2023 08:27:23 -0700 (PDT) Message-ID: <64381f5b.050a0220.1533e.41e2@mx.google.com> X-Google-Original-Message-ID: Date: Thu, 13 Apr 2023 10:27:21 -0500 From: Chris Morgan To: Sascha Hauer Subject: Re: [PATCH] drm/rockchip: vop2: fix suspend/resume References: <20230413144347.3506023-1-s.hauer@pengutronix.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230413144347.3506023-1-s.hauer@pengutronix.de> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?iso-8859-1?Q?K=F6ry?= Maincent , Sandy Huang , dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, Michael Riesch , kernel@pengutronix.de, stable@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Thu, Apr 13, 2023 at 04:43:47PM +0200, Sascha Hauer wrote: > During a suspend/resume cycle the VO power domain will be disabled and > the VOP2 registers will reset to their default values. After that the > cached register values will be out of sync and the read/modify/write > operations we do on the window registers will result in bogus values > written. Fix this by re-initializing the register cache each time we > enable the VOP2. With this the VOP2 will show a picture after a > suspend/resume cycle whereas without this the screen stays dark. > > Fixes: 604be85547ce4 ("drm/rockchip: Add VOP2 driver") > Cc: stable@vger.kernel.org > Signed-off-by: Sascha Hauer > --- > drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c > index ba3b817895091..d9daa686b014d 100644 > --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c > +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c > @@ -215,6 +215,8 @@ struct vop2 { > struct vop2_win win[]; > }; > > +static const struct regmap_config vop2_regmap_config; > + > static struct vop2_video_port *to_vop2_video_port(struct drm_crtc *crtc) > { > return container_of(crtc, struct vop2_video_port, crtc); > @@ -839,6 +841,12 @@ static void vop2_enable(struct vop2 *vop2) > return; > } > > + ret = regmap_reinit_cache(vop2->map, &vop2_regmap_config); > + if (ret) { > + drm_err(vop2->drm, "failed to reinit cache: %d\n", ret); > + return; > + } > + > if (vop2->data->soc_id == 3566) > vop2_writel(vop2, RK3568_OTP_WIN_EN, 1); > > -- > 2.39.2 > I confirmed this works on my Anbernic RG353P which uses the rk3566 SOC. Before applying the patch I displayed a color pattern with modetest before suspend and it appeared correctly. Then I suspended and resumed the device, attempted to display the same color pattern, and only got a single pixel on an otherwise blank display. After applying the patch I performed the same test and the color pattern appeared correctly both before and after suspend (and the display was no longer blank after resume from suspend). Tested-by: Chris Morgan