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Wed, 22 Oct 2025 21:05:31 +0000 Received: from SN7PR12MB8059.namprd12.prod.outlook.com ([fe80::4ee2:654e:1fe8:4b91]) by SN7PR12MB8059.namprd12.prod.outlook.com ([fe80::4ee2:654e:1fe8:4b91%2]) with mapi id 15.20.9228.015; Wed, 22 Oct 2025 21:05:31 +0000 Message-ID: <68f4bbff-56e1-4141-ad10-500a3a612a0e@nvidia.com> Date: Wed, 22 Oct 2025 17:05:29 -0400 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 5/7] gpu: nova-core: Add support for managing GSP falcon interrupts To: Alexandre Courbot , linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, dri-devel@lists.freedesktop.org, dakr@kernel.org Cc: Alistair Popple , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , bjorn3_gh@protonmail.com, Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , John Hubbard , Timur Tabi , joel@joelfernandes.org, Elle Rhumsaa , Daniel Almeida , nouveau@lists.freedesktop.org References: <20251020185539.49986-1-joelagnelf@nvidia.com> <20251020185539.49986-6-joelagnelf@nvidia.com> Content-Language: en-US From: Joel Fernandes In-Reply-To: Content-Type: text/plain; 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These are required for >> GSP message queue interrupt handling. >> >> Also rename clear_swgen0_intr() to enable_msq_interrupt() for >> readability. > > Let's make this "also" its own patch as it is a different thing. Sure, will do. To clarify, my intention was to make this a "prerequisite" patch series that's why it has all the goodies in a single series. However, it is probably less confusing to have them independently sent as you pointed out. >> Signed-off-by: Joel Fernandes >> --- >> drivers/gpu/nova-core/falcon/gsp.rs | 26 +++++++++++++++++++++++--- >> drivers/gpu/nova-core/gpu.rs | 2 +- >> drivers/gpu/nova-core/regs.rs | 10 ++++++++++ >> 3 files changed, 34 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/gpu/nova-core/falcon/gsp.rs b/drivers/gpu/nova-core/falcon/gsp.rs >> index f17599cb49fa..6da63823996b 100644 >> --- a/drivers/gpu/nova-core/falcon/gsp.rs >> +++ b/drivers/gpu/nova-core/falcon/gsp.rs >> @@ -22,11 +22,31 @@ impl FalconEngine for Gsp { >> } >> >> impl Falcon { >> - /// Clears the SWGEN0 bit in the Falcon's IRQ status clear register to >> - /// allow GSP to signal CPU for processing new messages in message queue. >> - pub(crate) fn clear_swgen0_intr(&self, bar: &Bar0) { >> + /// Enable the GSP Falcon message queue interrupt (SWGEN0 interrupt). >> + #[expect(dead_code)] >> + pub(crate) fn enable_msgq_interrupt(&self, bar: &Bar0) { >> + regs::NV_PFALCON_FALCON_IRQMASK::alter(bar, &Gsp::ID, |r| r.set_swgen0(true)); >> + } >> + >> + /// Check if the message queue interrupt is pending. >> + #[expect(dead_code)] >> + pub(crate) fn has_msgq_interrupt(&self, bar: &Bar0) -> bool { >> + regs::NV_PFALCON_FALCON_IRQSTAT::read(bar, &Gsp::ID).swgen0() >> + } >> + >> + /// Clears the message queue interrupt to allow GSP to signal CPU >> + /// for processing new messages. >> + pub(crate) fn clear_msgq_interrupt(&self, bar: &Bar0) { >> regs::NV_PFALCON_FALCON_IRQSCLR::default() >> .set_swgen0(true) >> .write(bar, &Gsp::ID); >> } >> + >> + /// Acknowledge all pending GSP interrupts. >> + #[expect(dead_code)] >> + pub(crate) fn ack_all_interrupts(&self, bar: &Bar0) { >> + // Read status and write the raw value to IRQSCLR to clear all pending interrupts. >> + let status = regs::NV_PFALCON_FALCON_IRQSTAT::read(bar, &Gsp::ID); >> + regs::NV_PFALCON_FALCON_IRQSCLR::from(u32::from(status)).write(bar, &Gsp::ID); >> + } > > I think this can be a bit more generic than that: all interrupts for all > falcons are handled the same way, so we shouldn't need to write > `enable`, `clear`, and other methods for each. > > So the first step should probably be a generic `impl Falcon` block > that provides base methods for specialized blocks to reuse. It could > work with just the index of the bit corresponding to the interrupt to > enable/clear, but if we want to involve the type system we could also > define a `FalconInterrupt` trait with an associated type for the engine > on which this interrupt is valid, and its bit index as an associated > const. > > But I suspect that the set of interrupts is going to be pretty standard, > so maybe we can use the standard nomenclature for the generic methods > (i.e. SWGEN0), and have dedicated methods for specialized units where > relevant. Good point. I'll start with the `impl Falcon` block as it is simple. I also suspect as you do that the layout should be standard across falcons. Thanks for the suggestion and reviews. thanks, - Joel