From: Nancy.Lin <nancy.lin@mediatek.com>
To: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Cc: CK Hu <ck.hu@mediatek.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
"David Airlie" <airlied@linux.ie>,
Daniel Vetter <daniel@ffwll.ch>, Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
"jason-jh . lin" <jason-jh.lin@mediatek.com>,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
DRI Development <dri-devel@lists.freedesktop.org>,
"moderated list:ARM/Mediatek SoC support"
<linux-mediatek@lists.infradead.org>,
DTML <devicetree@vger.kernel.org>,
linux-kernel <linux-kernel@vger.kernel.org>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
<singo.chang@mediatek.com>,
srv_heupstream <srv_heupstream@mediatek.com>
Subject: Re: [PATCH v6 12/16] drm/mediatek: add display merge api support for MT8195
Date: Mon, 25 Oct 2021 10:10:24 +0800 [thread overview]
Message-ID: <6f55c349e1325635198795d1a67c302bdcadd9ac.camel@mediatek.com> (raw)
In-Reply-To: <CAAOTY_-wwXHMq4fB9wNGub=Sh-Ep3aOJJPaNTch2zebhZzEvkA@mail.gmail.com>
Hi Chun-Kuang,
Thanks for the review.
On Thu, 2021-10-21 at 23:02 +0800, Chun-Kuang Hu wrote:
> >
> Hi, Nancy:
>
> Nancy.Lin <nancy.lin@mediatek.com> 於 2021年10月4日 週一 下午2:21寫道:
> >
> > Add merge new API.
> > 1. Vdosys1 merge1~merge4 support HW mute function, so add unmute
> > API.
> > 2. Add merge new advance config API. The original merge API is
> > mtk_ddp_comp_funcs function prototype. The API interface
> > parameters
> > cannot be modified, so add a new config API for extension.
> > 3. Add merge enable/disable API for cmdq support. The ovl_adaptor
> > merges
> > are configured with each drm plane update. Need to
> > enable/disable
> > merge with cmdq making sure all the settings taken effect in the
> > same vblank.
>
> Separate this patch into three patches.
>
OK.
> > Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 6 ++
> > drivers/gpu/drm/mediatek/mtk_disp_merge.c | 86
> > ++++++++++++++++++++---
> > 2 files changed, 82 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index b3a372cab0bd..2446ad0a4977 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -63,6 +63,12 @@ void mtk_merge_config(struct device *dev,
> > unsigned int width,
> > unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> > void mtk_merge_start(struct device *dev);
> > void mtk_merge_stop(struct device *dev);
> > +void mtk_merge_advance_config(struct device *dev, unsigned int
> > l_w, unsigned int r_w,
> > + unsigned int h, unsigned int
> > vrefresh, unsigned int bpc,
> > + struct cmdq_pkt *cmdq_pkt);
> > +void mtk_merge_unmute(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt);
> > +void mtk_merge_enable(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt);
> > +void mtk_merge_disable(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt);
> >
> > void mtk_ovl_bgclr_in_on(struct device *dev);
> > void mtk_ovl_bgclr_in_off(struct device *dev);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > index b05e1df79c3d..696bb948352b 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > @@ -17,6 +17,7 @@
> > #define DISP_REG_MERGE_CTRL 0x000
> > #define MERGE_EN 1
> > #define DISP_REG_MERGE_CFG_0 0x010
> > +#define DISP_REG_MERGE_CFG_1 0x014
> > #define DISP_REG_MERGE_CFG_4 0x020
> > #define DISP_REG_MERGE_CFG_10 0x038
> > /* no swap */
> > @@ -25,9 +26,12 @@
> > #define DISP_REG_MERGE_CFG_12 0x040
> > #define CFG_10_10_1PI_2PO_BUF_MODE 6
> > #define CFG_10_10_2PI_2PO_BUF_MODE 8
> > +#define CFG_11_10_1PI_2PO_MERGE 18
> > #define FLD_CFG_MERGE_MODE GENMASK(4, 0)
> > #define DISP_REG_MERGE_CFG_24 0x070
> > #define DISP_REG_MERGE_CFG_25 0x074
> > +#define DISP_REG_MERGE_CFG_26 0x078
> > +#define DISP_REG_MERGE_CFG_27 0x07c
> > #define DISP_REG_MERGE_CFG_36 0x0a0
> > #define ULTRA_EN BIT(0)
> > #define PREULTRA_EN BIT(4)
> > @@ -54,26 +58,52 @@
> > #define FLD_PREULTRA_TH_LOW GENMASK(15, 0)
> > #define FLD_PREULTRA_TH_HIGH GENMASK(31, 16)
> >
> > +#define DISP_REG_MERGE_MUTE_0 0xf00
> > +
> > struct mtk_disp_merge {
> > void __iomem *regs;
> > struct clk *clk;
> > struct clk *async_clk;
> > struct cmdq_client_reg cmdq_reg;
> > bool fifo_en;
> > + bool mute_support;
>
> Align indent of members.
>
OK.
> > };
> >
> > void mtk_merge_start(struct device *dev)
> > +{
> > + mtk_merge_enable(dev, NULL);
> > +}
> > +
> > +void mtk_merge_stop(struct device *dev)
> > {
> > struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> >
> > - writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
> > + mtk_merge_disable(dev, NULL);
> > }
> >
> > -void mtk_merge_stop(struct device *dev)
> > +void mtk_merge_enable(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt)
>
> The difference of mtk_merge_enable() and mtk_merge_start() is cmdq
> support, but the naming make them so different. So I would like this
> function name to be mtk_merge_start_cmdq().
>
OK.
> > +{
> > + struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > + mtk_ddp_write(cmdq_pkt, 1, &priv->cmdq_reg, priv->regs,
> > + DISP_REG_MERGE_CTRL);
> > +}
> > +
> > +void mtk_merge_disable(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt)
>
> Ditto.
OK.
>
> > {
> > struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> >
> > - writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
> > + mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs,
> > + DISP_REG_MERGE_CTRL);
> > +}
> > +
> > +void mtk_merge_unmute(struct device *dev, struct cmdq_pkt
> > *cmdq_pkt)
>
> I'm not sure whether it's worth to have this function. It seems that
> mtk_merge_enable() imply mtk_merge_unmute(). So I would like to move
> this function into mtk_merge_enable().
> And I would like to mute in mtk_merge_disable() to let register be
> restored.
>
> Regards,
> Chun-Kuang.
>
OK. I will remove the unmute API, and move unmute function into merge
start/stop.
> > +{
> > + struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > + if (priv->mute_support)
> > + mtk_ddp_write(cmdq_pkt, 0x0, &priv->cmdq_reg, priv-
> > >regs,
> > + DISP_REG_MERGE_MUTE_0);
> > }
> >
> > static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
> > @@ -98,12 +128,19 @@ static void mtk_merge_fifo_setting(struct
> > mtk_disp_merge *priv,
> > void mtk_merge_config(struct device *dev, unsigned int w,
> > unsigned int h, unsigned int vrefresh,
> > unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
> > +{
> > + mtk_merge_advance_config(dev, w, 0, h, vrefresh, bpc,
> > cmdq_pkt);
> > +}
> > +
> > +void mtk_merge_advance_config(struct device *dev, unsigned int
> > l_w, unsigned int r_w,
> > + unsigned int h, unsigned int
> > vrefresh, unsigned int bpc,
> > + struct cmdq_pkt *cmdq_pkt)
> > {
> > struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
> >
> > - if (!h || !w) {
> > - dev_err(dev, "%s: input width(%d) or height(%d) is
> > invalid\n", __func__, w, h);
> > + if (!h || !l_w) {
> > + dev_err(dev, "%s: input width(%d) or height(%d) is
> > invalid\n", __func__, l_w, h);
> > return;
> > }
> >
> > @@ -112,14 +149,41 @@ void mtk_merge_config(struct device *dev,
> > unsigned int w,
> > mode = CFG_10_10_2PI_2PO_BUF_MODE;
> > }
> >
> > - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs,
> > + if (r_w)
> > + mode = CFG_11_10_1PI_2PO_MERGE;
> > +
> > + mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg,
> > priv->regs,
> > DISP_REG_MERGE_CFG_0);
> > - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs,
> > + mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg,
> > priv->regs,
> > + DISP_REG_MERGE_CFG_1);
> > + mtk_ddp_write(cmdq_pkt, h << 16 | (l_w + r_w), &priv-
> > >cmdq_reg, priv->regs,
> > DISP_REG_MERGE_CFG_4);
> > - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs,
> > + /*
> > + * DISP_REG_MERGE_CFG_24 is merge SRAM0 w/h
> > + * DISP_REG_MERGE_CFG_25 is merge SRAM1 w/h.
> > + * If r_w > 0, the merge is in merge mode (input0 and
> > input1 merge together),
> > + * the input0 goes to SRAM0, and input1 goes to SRAM1.
> > + * If r_w = 0, the merge is in buffer mode, the input goes
> > through SRAM0 and
> > + * then to SRAM1. Both SRAM0 and SRAM1 are set to the same
> > size.
> > + */
> > + mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg,
> > priv->regs,
> > DISP_REG_MERGE_CFG_24);
> > - mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv-
> > >regs,
> > - DISP_REG_MERGE_CFG_25);
> > + if (r_w)
> > + mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv-
> > >cmdq_reg, priv->regs,
> > + DISP_REG_MERGE_CFG_25);
> > + else
> > + mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv-
> > >cmdq_reg, priv->regs,
> > + DISP_REG_MERGE_CFG_25);
> > +
> > + /*
> > + * DISP_REG_MERGE_CFG_26 and DISP_REG_MERGE_CFG_27 is only
> > used in LR merge.
> > + * Only take effect when the merge is setting to merge
> > mode.
> > + */
> > + mtk_ddp_write(cmdq_pkt, h << 16 | l_w, &priv->cmdq_reg,
> > priv->regs,
> > + DISP_REG_MERGE_CFG_26);
> > + mtk_ddp_write(cmdq_pkt, h << 16 | r_w, &priv->cmdq_reg,
> > priv->regs,
> > + DISP_REG_MERGE_CFG_27);
> > +
> > mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg,
> > priv->regs,
> > DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
> > mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv-
> > >regs,
> > @@ -205,6 +269,8 @@ static int mtk_disp_merge_probe(struct
> > platform_device *pdev)
> > priv->fifo_en = of_property_read_bool(dev->of_node,
> > "mediatek,merge-fifo-
> > en");
> >
> > + priv->mute_support = of_property_read_bool(dev->of_node,
> > + "mediatek,merge-
> > mute");
> > platform_set_drvdata(pdev, priv);
> >
> > ret = component_add(dev, &mtk_disp_merge_component_ops);
> > --
> > 2.18.0
> >
next prev parent reply other threads:[~2021-10-25 2:10 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-04 6:21 [PATCH v6 00/16] Add MediaTek SoC DRM (vdosys1) support for mt8195 Nancy.Lin
2021-10-04 6:21 ` [PATCH v6 01/16] dt-bindings: mediatek: add vdosys1 RDMA definition " Nancy.Lin
2021-10-04 6:21 ` [PATCH v6 02/16] dt-bindings: mediatek: add vdosys1 MERGE property " Nancy.Lin
2021-10-15 8:08 ` AngeloGioacchino Del Regno
2021-10-15 16:21 ` Chun-Kuang Hu
2021-10-04 6:21 ` [PATCH v6 03/16] dt-bindings: mediatek: add ethdr definition " Nancy.Lin
2021-10-15 23:37 ` Chun-Kuang Hu
2021-10-22 7:18 ` Nancy.Lin
2021-10-04 6:21 ` [PATCH v6 04/16] dt-bindings: reset: mt8195: add vdosys1 reset control bit Nancy.Lin
2021-10-15 23:41 ` Chun-Kuang Hu
2021-10-04 6:21 ` [PATCH v6 05/16] arm64: dts: mt8195: add display node for vdosys1 Nancy.Lin
2021-10-04 6:21 ` [PATCH v6 06/16] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1 Nancy.Lin
2021-10-14 14:52 ` AngeloGioacchino Del Regno
2021-10-04 6:21 ` [PATCH v6 07/16] soc: mediatek: add mtk-mmsys config API " Nancy.Lin
2021-10-04 6:21 ` [PATCH v6 08/16] soc: mediatek: add cmdq support of " Nancy.Lin
2021-10-04 6:21 ` [PATCH v6 09/16] soc: mediatek: mmsys: modify reset controller for MT8195 vdosys1 Nancy.Lin
2021-10-14 14:56 ` AngeloGioacchino Del Regno
2021-10-22 7:05 ` Nancy.Lin
2021-10-04 6:21 ` [PATCH v6 10/16] soc: mediatek: add mtk-mutex support for mt8195 vdosys1 Nancy.Lin
2021-10-14 15:01 ` AngeloGioacchino Del Regno
2021-10-22 7:33 ` Nancy.Lin
2021-10-04 6:21 ` [PATCH v6 11/16] drm/mediatek: add display MDP RDMA support for MT8195 Nancy.Lin
2021-10-19 16:38 ` Chun-Kuang Hu
2021-10-25 1:48 ` Nancy.Lin
2021-10-04 6:21 ` [PATCH v6 12/16] drm/mediatek: add display merge api " Nancy.Lin
2021-10-21 15:02 ` Chun-Kuang Hu
2021-10-25 2:10 ` Nancy.Lin [this message]
2021-10-04 6:21 ` [PATCH v6 13/16] drm/mediatek: add ETHDR " Nancy.Lin
2021-10-21 15:44 ` Chun-Kuang Hu
2021-10-25 2:24 ` Nancy.Lin
2021-10-04 6:21 ` [PATCH v6 14/16] drm/mediatek: add ovl_adaptor " Nancy.Lin
2021-10-15 7:49 ` AngeloGioacchino Del Regno
2021-10-25 2:42 ` Nancy.Lin
2021-10-25 23:11 ` Chun-Kuang Hu
2021-10-26 7:53 ` Nancy.Lin
2021-10-04 6:21 ` [PATCH v6 15/16] drm/mediatek: modify mediatek-drm for mt8195 multi mmsys support Nancy.Lin
2021-10-04 6:21 ` [PATCH v6 16/16] drm/mediatek: add mediatek-drm of vdosys1 support for MT8195 Nancy.Lin
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