[PATCH v2 0/4] Support for Adreno X1-45 GPU

[PATCH v2 0/4] Support for Adreno X1-45 GPU

[Akhil P Oommen]

Add support for X1-45 GPU found in X1P41200 chipset (8 cpu core
version). X1-45 is a smaller version of X1-85 with lower core count and
smaller memories. From UMD perspective, this is similar to "FD735"
present in Mesa.

Tested Glmark & Vkmark on Debian Gnome desktop.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
Changes in v2:
- Skip 'delete-property' wherever it is unnecessary (Dmitry)
- Reorder dt nodes alphabetically (Konrad)
- A new patch#1 to fix the dtbs_check error
- Link to v1: https://lore.kernel.org/r/20250607-x1p-adreno-v1-0-a8ea80f3b18b@oss.qualcomm.com

---
Akhil P Oommen (4):
      dt-bindings: opp: adreno: Update regex of OPP entry
      arm64: defconfig: Enable X1P42100_GPUCC driver
      drm/msm/adreno: Add Adreno X1-45 support
      arm64: dts: qcom: Add GPU support to X1P42100 SoC

 .../bindings/opp/opp-v2-qcom-adreno.yaml           |   2 +-
 arch/arm64/boot/dts/qcom/x1e80100.dtsi             |   7 ++
 arch/arm64/boot/dts/qcom/x1p42100-crd.dts          |   4 +
 arch/arm64/boot/dts/qcom/x1p42100.dtsi             | 120 ++++++++++++++++++++-
 arch/arm64/configs/defconfig                       |   1 +
 drivers/gpu/drm/msm/adreno/a6xx_catalog.c          |  38 +++++++
 6 files changed, 169 insertions(+), 3 deletions(-)
---
base-commit: b3bded85d838336326ce78e394e7818445e11f20
change-id: 20250603-x1p-adreno-219da2fd4ca4

Best regards,
-- 
Akhil P Oommen <akhilpo@oss.qualcomm.com>

[PATCH v2 1/4] dt-bindings: opp: adreno: Update regex of OPP entry

[Akhil P Oommen]

Update regex to allow multi-worded OPP entry names.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
 Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml b/Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml
index a27ba7b663d456f964628a91a661b51a684de1be..bba95799919eb52d12afa42354ed909d0ef3c627 100644
--- a/Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml
+++ b/Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml
@@ -23,7 +23,7 @@ properties:
       const: operating-points-v2-adreno
 
 patternProperties:
-  '^opp-[0-9]+$':
+  '^opp(-?[0-9]+)*$':
     type: object
     additionalProperties: false
 

-- 
2.48.1

Re: [PATCH v2 1/4] dt-bindings: opp: adreno: Update regex of OPP entry

[Krzysztof Kozlowski]

On 11/06/2025 13:15, Akhil P Oommen wrote:
> Update regex to allow multi-worded OPP entry names.

Why would we want multi-worded? This needs to be explained here.


> 
> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
> ---
>  Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml b/Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml
> index a27ba7b663d456f964628a91a661b51a684de1be..bba95799919eb52d12afa42354ed909d0ef3c627 100644
> --- a/Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml
> +++ b/Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml
> @@ -23,7 +23,7 @@ properties:
>        const: operating-points-v2-adreno
>  
>  patternProperties:
> -  '^opp-[0-9]+$':
> +  '^opp(-?[0-9]+)*$':

Not correct regex. You allow "opp", "opp1" and all other unusual
variants. Commit does not explain what problem you are solving, so I
have no clue what you want here, but for sure opp1 is wrong.


Best regards,
Krzysztof

Re: [PATCH v2 1/4] dt-bindings: opp: adreno: Update regex of OPP entry

[Akhil P Oommen]

On 6/11/2025 4:50 PM, Krzysztof Kozlowski wrote:
> On 11/06/2025 13:15, Akhil P Oommen wrote:
>> Update regex to allow multi-worded OPP entry names.
> 
> Why would we want multi-worded? This needs to be explained here.

I took the new regex from "opp-v2-base.yaml" file, so I thought it was
obvious enough. The requirement is that sometimes Adreno GPU may require
variants of OPP entries with same frequency. As an example, we may want
to vote different peak bandwidths in different SKUs for the same GPU
frequency. So to denote this minor variation, we can add an integer
suffix to the OPP entry name separated by '-'. An example from another
patch in this series:

 opp-666000000-0 {
         opp-hz = /bits/ 64 <666000000>;
         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
         opp-peak-kBps = <8171875>;
         qcom,opp-acd-level = <0xa82d5ffd>;
         opp-supported-hw = <0xf>;
 };

 /* Only applicable for SKUs which has 666Mhz as Fmax */
 opp-666000000-1 {
         opp-hz = /bits/ 64 <666000000>;
         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
         opp-peak-kBps = <16500000>;
         qcom,opp-acd-level = <0xa82d5ffd>;
         opp-supported-hw = <0x10>;
 };

I will add this explanation in the commit text in the next revision.

> 
> 
>>
>> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
>> ---
>>  Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml b/Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml
>> index a27ba7b663d456f964628a91a661b51a684de1be..bba95799919eb52d12afa42354ed909d0ef3c627 100644
>> --- a/Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml
>> +++ b/Documentation/devicetree/bindings/opp/opp-v2-qcom-adreno.yaml
>> @@ -23,7 +23,7 @@ properties:
>>        const: operating-points-v2-adreno
>>  
>>  patternProperties:
>> -  '^opp-[0-9]+$':
>> +  '^opp(-?[0-9]+)*$':
> 
> Not correct regex. You allow "opp", "opp1" and all other unusual
> variants. Commit does not explain what problem you are solving, so I
> have no clue what you want here, but for sure opp1 is wrong.

Just to confirm, would this be fine for the requirement I mentioned above?

"'^opp(-[0-9]+)*$'"

-Akhil.

> 
> 
> Best regards,
> Krzysztof

Re: [PATCH v2 1/4] dt-bindings: opp: adreno: Update regex of OPP entry

[Krzysztof Kozlowski]

On 11/06/2025 14:24, Akhil P Oommen wrote:
>>>  
>>>  patternProperties:
>>> -  '^opp-[0-9]+$':
>>> +  '^opp(-?[0-9]+)*$':
>>
>> Not correct regex. You allow "opp", "opp1" and all other unusual
>> variants. Commit does not explain what problem you are solving, so I
>> have no clue what you want here, but for sure opp1 is wrong.
> 
> Just to confirm, would this be fine for the requirement I mentioned above?
> 
> "'^opp(-[0-9]+)*$'"

No, You did not solve half of the problems - still allows "opp" and
commit msg does not explain why "opp" is now correct. Describe the
actual problem and then write the regex solving it in specific way, not
causing other effects.

Best regards,
Krzysztof

Re: [PATCH v2 1/4] dt-bindings: opp: adreno: Update regex of OPP entry

[Akhil P Oommen]

On 6/12/2025 4:59 PM, Krzysztof Kozlowski wrote:
> On 11/06/2025 14:24, Akhil P Oommen wrote:
>>>>  
>>>>  patternProperties:
>>>> -  '^opp-[0-9]+$':
>>>> +  '^opp(-?[0-9]+)*$':
>>>
>>> Not correct regex. You allow "opp", "opp1" and all other unusual
>>> variants. Commit does not explain what problem you are solving, so I
>>> have no clue what you want here, but for sure opp1 is wrong.
>>
>> Just to confirm, would this be fine for the requirement I mentioned above?
>>
>> "'^opp(-[0-9]+)*$'"
> 
> No, You did not solve half of the problems - still allows "opp" and
> commit msg does not explain why "opp" is now correct. Describe the
> actual problem and then write the regex solving it in specific way, not
> causing other effects.

Gotcha. If we want to be super strict, the regex should be:
^opp(-[0-9]+){1,2}$

I will send out a new patch.

-Akhil

> 
> Best regards,
> Krzysztof

Re: [PATCH v2 1/4] dt-bindings: opp: adreno: Update regex of OPP entry

[Krzysztof Kozlowski]

On Mon, Jun 16, 2025 at 10:18:24PM GMT, Akhil P Oommen wrote:
> On 6/12/2025 4:59 PM, Krzysztof Kozlowski wrote:
> > On 11/06/2025 14:24, Akhil P Oommen wrote:
> >>>>  
> >>>>  patternProperties:
> >>>> -  '^opp-[0-9]+$':
> >>>> +  '^opp(-?[0-9]+)*$':
> >>>
> >>> Not correct regex. You allow "opp", "opp1" and all other unusual
> >>> variants. Commit does not explain what problem you are solving, so I
> >>> have no clue what you want here, but for sure opp1 is wrong.
> >>
> >> Just to confirm, would this be fine for the requirement I mentioned above?
> >>
> >> "'^opp(-[0-9]+)*$'"
> > 
> > No, You did not solve half of the problems - still allows "opp" and
> > commit msg does not explain why "opp" is now correct. Describe the
> > actual problem and then write the regex solving it in specific way, not
> > causing other effects.
> 
> Gotcha. If we want to be super strict, the regex should be:
> ^opp(-[0-9]+){1,2}$
> 

Yes, looks good.

Best regards,
Krzysztof

[PATCH v2 2/4] arm64: defconfig: Enable X1P42100_GPUCC driver

[Akhil P Oommen]

In order to enable GPU support in Snapdragon X1P42100
(8 CPU core version found on Asus Zenbook A14 and other
similar laptops), enable X1P42100 GPUCC driver as a module.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 62d3c87858e1817bac291780dff3823dacd72510..9cc473fd0d3308f7869d00425e17b114c87093b2 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1350,6 +1350,7 @@ CONFIG_CLK_X1E80100_CAMCC=m
 CONFIG_CLK_X1E80100_DISPCC=m
 CONFIG_CLK_X1E80100_GCC=y
 CONFIG_CLK_X1E80100_GPUCC=m
+CONFIG_CLK_X1P42100_GPUCC=m
 CONFIG_CLK_X1E80100_TCSRCC=y
 CONFIG_CLK_QCM2290_GPUCC=m
 CONFIG_QCOM_A53PLL=y

-- 
2.48.1

Re: [PATCH v2 2/4] arm64: defconfig: Enable X1P42100_GPUCC driver

[Krzysztof Kozlowski]

On 11/06/2025 13:15, Akhil P Oommen wrote:
> In order to enable GPU support in Snapdragon X1P42100
> (8 CPU core version found on Asus Zenbook A14 and other

There is no A14 upstream board DTS in next. Your commit msg should
provide rationale for this, e.g. which upstream boards use this driver.

Best regards,
Krzysztof

Re: [PATCH v2 2/4] arm64: defconfig: Enable X1P42100_GPUCC driver

[Akhil P Oommen]

On 6/11/2025 4:55 PM, Krzysztof Kozlowski wrote:
> On 11/06/2025 13:15, Akhil P Oommen wrote:
>> In order to enable GPU support in Snapdragon X1P42100
>> (8 CPU core version found on Asus Zenbook A14 and other
> 
> There is no A14 upstream board DTS in next. Your commit msg should
> provide rationale for this, e.g. which upstream boards use this driver.
> 

Will replace "Asus Zenbook" with "X1P42100 CRD" which is supported upstream.

-Akhil.

> Best regards,
> Krzysztof

[PATCH v2 3/4] drm/msm/adreno: Add Adreno X1-45 support

[Akhil P Oommen]

Add support for Adreno X1-45 GPU present Snapdragon X1P42100
series of compute chipsets. This GPU is a smaller version of
X1-85 GPU with lower core count and smaller internal memories.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
 drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 38 +++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 70f7ad806c34076352d84f32d62c2833422b6e5e..2db748ce7df57a9151ed1e7f1b025a537bb5f653 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -1474,6 +1474,44 @@ static const struct adreno_info a7xx_gpus[] = {
 			},
 		},
 		.preempt_record_size = 3572 * SZ_1K,
+	}, {
+		.chip_ids = ADRENO_CHIP_IDS(0x43030c00),
+		.family = ADRENO_7XX_GEN2,
+		.fw = {
+			[ADRENO_FW_SQE] = "gen71500_sqe.fw",
+			[ADRENO_FW_GMU] = "gen71500_gmu.bin",
+		},
+		.gmem = SZ_1M + SZ_512K,
+		.inactive_period = DRM_MSM_INACTIVE_PERIOD,
+		.quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT |
+			  ADRENO_QUIRK_HAS_HW_APRIV |
+			  ADRENO_QUIRK_PREEMPTION,
+		.init = a6xx_gpu_init,
+		.a6xx = &(const struct a6xx_info) {
+			.hwcg = a740_hwcg,
+			.protect = &a730_protect,
+			.pwrup_reglist = &a7xx_pwrup_reglist,
+			.gmu_chipid = 0x70f0000,
+			.gmu_cgc_mode = 0x00020222,
+			.bcms = (const struct a6xx_bcm[]) {
+				{ .name = "SH0", .buswidth = 16 },
+				{ .name = "MC0", .buswidth = 4 },
+				{
+					.name = "ACV",
+					.fixed = true,
+					.perfmode = BIT(3),
+					.perfmode_bw = 16500000,
+				},
+				{ /* sentinel */ },
+			},
+		},
+		.preempt_record_size = 4192 * SZ_1K,
+		.speedbins = ADRENO_SPEEDBINS(
+			{ 0,   0 },
+			{ 294, 1 },
+			{ 263, 2 },
+			{ 141, 3 },
+		),
 	}
 };
 DECLARE_ADRENO_GPULIST(a7xx);

-- 
2.48.1

[PATCH v2 4/4] arm64: dts: qcom: Add GPU support to X1P42100 SoC

[Akhil P Oommen]

X1P42100 SoC has a new GPU called Adreno X1-45 which is a smaller
version of Adreno X1-85 GPU. Describe this new GPU and also add
the secure gpu firmware path that should used for X1P42100 CRD.

Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/x1e80100.dtsi    |   7 ++
 arch/arm64/boot/dts/qcom/x1p42100-crd.dts |   4 +
 arch/arm64/boot/dts/qcom/x1p42100.dtsi    | 120 +++++++++++++++++++++++++++++-
 3 files changed, 129 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index a8eb4c5fe99fe6dd49af200a738b6476d87279b2..558d7d387d7710770244fcc901f461384dd9b0d4 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -8245,6 +8245,13 @@ sbsa_watchdog: watchdog@1c840000 {
 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		qfprom: efuse@221c8000 {
+			compatible = "qcom,x1e80100-qfprom", "qcom,qfprom";
+			reg = <0 0x221c8000 0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+
 		pmu@24091000 {
 			compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
 			reg = <0 0x24091000 0 0x1000>;
diff --git a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts
index cf07860a63e97c388909fb5721ae7b9729b6c586..cf999c2cf8d4e0af83078253fd39ece3a0c26a49 100644
--- a/arch/arm64/boot/dts/qcom/x1p42100-crd.dts
+++ b/arch/arm64/boot/dts/qcom/x1p42100-crd.dts
@@ -15,3 +15,7 @@ / {
 	model = "Qualcomm Technologies, Inc. X1P42100 CRD";
 	compatible = "qcom,x1p42100-crd", "qcom,x1p42100";
 };
+
+&gpu_zap_shader {
+	firmware-name = "qcom/x1p42100/gen71500_zap.mbn";
+};
diff --git a/arch/arm64/boot/dts/qcom/x1p42100.dtsi b/arch/arm64/boot/dts/qcom/x1p42100.dtsi
index 27f479010bc330eb6445269a1c46bf78ec6f1bd4..807db5a079394442596939847e0e6aef4b0525a1 100644
--- a/arch/arm64/boot/dts/qcom/x1p42100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1p42100.dtsi
@@ -17,15 +17,124 @@
 /delete-node/ &cpu_pd9;
 /delete-node/ &cpu_pd10;
 /delete-node/ &cpu_pd11;
+/delete-node/ &gpu_opp_table;
 /delete-node/ &pcie3_phy;
 
 &gcc {
 	compatible = "qcom,x1p42100-gcc", "qcom,x1e80100-gcc";
 };
 
-/* The GPU is physically different and will be brought up later */
+&gmu {
+	compatible = "qcom,adreno-gmu-x145.0", "qcom,adreno-gmu";
+};
+
 &gpu {
-	/delete-property/ compatible;
+	compatible = "qcom,adreno-43030c00", "qcom,adreno";
+
+	nvmem-cells = <&gpu_speed_bin>;
+	nvmem-cell-names = "speed_bin";
+
+	gpu_opp_table: opp-table {
+		compatible = "operating-points-v2-adreno", "operating-points-v2";
+
+		opp-1400000000 {
+			opp-hz = /bits/ 64 <1400000000>;
+			opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
+			opp-peak-kBps = <16500000>;
+			qcom,opp-acd-level = <0xa8295ffd>;
+			opp-supported-hw = <0x3>;
+		};
+
+		opp-1250000000 {
+			opp-hz = /bits/ 64 <1250000000>;
+			opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
+			opp-peak-kBps = <16500000>;
+			qcom,opp-acd-level = <0x882a5ffd>;
+			opp-supported-hw = <0x7>;
+		};
+
+		opp-1107000000 {
+			opp-hz = /bits/ 64 <1107000000>;
+			opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+			opp-peak-kBps = <16500000>;
+			qcom,opp-acd-level = <0x882a5ffd>;
+			opp-supported-hw = <0xf>;
+		};
+
+		opp-1014000000 {
+			opp-hz = /bits/ 64 <1014000000>;
+			opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+			opp-peak-kBps = <14398438>;
+			qcom,opp-acd-level = <0xa82a5ffd>;
+			opp-supported-hw = <0xf>;
+		};
+
+		opp-940000000 {
+			opp-hz = /bits/ 64 <940000000>;
+			opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+			opp-peak-kBps = <14398438>;
+			qcom,opp-acd-level = <0xa82a5ffd>;
+			opp-supported-hw = <0xf>;
+		};
+
+		opp-825000000 {
+			opp-hz = /bits/ 64 <825000000>;
+			opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+			opp-peak-kBps = <12449219>;
+			qcom,opp-acd-level = <0x882b5ffd>;
+			opp-supported-hw = <0xf>;
+		};
+
+		opp-720000000 {
+			opp-hz = /bits/ 64 <720000000>;
+			opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+			opp-peak-kBps = <10687500>;
+			qcom,opp-acd-level = <0xa82c5ffd>;
+			opp-supported-hw = <0xf>;
+		};
+
+		opp-666000000-0 {
+			opp-hz = /bits/ 64 <666000000>;
+			opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+			opp-peak-kBps = <8171875>;
+			qcom,opp-acd-level = <0xa82d5ffd>;
+			opp-supported-hw = <0xf>;
+		};
+
+		/* Only applicable for SKUs which has 666Mhz as Fmax */
+		opp-666000000-1 {
+			opp-hz = /bits/ 64 <666000000>;
+			opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+			opp-peak-kBps = <16500000>;
+			qcom,opp-acd-level = <0xa82d5ffd>;
+			opp-supported-hw = <0x10>;
+		};
+
+		opp-550000000 {
+			opp-hz = /bits/ 64 <550000000>;
+			opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+			opp-peak-kBps = <6074219>;
+			qcom,opp-acd-level = <0x882e5ffd>;
+			opp-supported-hw = <0x1f>;
+		};
+
+		opp-380000000 {
+			opp-hz = /bits/ 64 <380000000>;
+			opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+			opp-peak-kBps = <3000000>;
+			qcom,opp-acd-level = <0xc82f5ffd>;
+			opp-supported-hw = <0x1f>;
+		};
+
+		opp-280000000 {
+			opp-hz = /bits/ 64 <280000000>;
+			opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
+			opp-peak-kBps = <2136719>;
+			qcom,opp-acd-level = <0xc82f5ffd>;
+			opp-supported-hw = <0x1f>;
+		};
+	};
+
 };
 
 &gpucc {
@@ -41,6 +150,13 @@ &pcie6a_phy {
 	compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy";
 };
 
+&qfprom {
+	gpu_speed_bin: gpu_speed_bin@119 {
+		reg = <0x119 0x2>;
+		bits = <7 9>;
+	};
+};
+
 &soc {
 	/* The PCIe3 PHY on X1P42100 uses a different IP block */
 	pcie3_phy: phy@1bd4000 {

-- 
2.48.1

Re: [PATCH v2 4/4] arm64: dts: qcom: Add GPU support to X1P42100 SoC

[Krzysztof Kozlowski]

On 11/06/2025 13:15, Akhil P Oommen wrote:
> +		opp-280000000 {
> +			opp-hz = /bits/ 64 <280000000>;
> +			opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
> +			opp-peak-kBps = <2136719>;
> +			qcom,opp-acd-level = <0xc82f5ffd>;
> +			opp-supported-hw = <0x1f>;
> +		};
> +	};
> +
>  };
>  
>  &gpucc {
> @@ -41,6 +150,13 @@ &pcie6a_phy {
>  	compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy";
>  };
>  
> +&qfprom {
> +	gpu_speed_bin: gpu_speed_bin@119 {

No underscores. You need to align downstream code to upstream. See
coding style.



Best regards,
Krzysztof

Re: [PATCH v2 4/4] arm64: dts: qcom: Add GPU support to X1P42100 SoC

[Akhil P Oommen]

On 6/11/2025 4:52 PM, Krzysztof Kozlowski wrote:
> On 11/06/2025 13:15, Akhil P Oommen wrote:
>> +		opp-280000000 {
>> +			opp-hz = /bits/ 64 <280000000>;
>> +			opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
>> +			opp-peak-kBps = <2136719>;
>> +			qcom,opp-acd-level = <0xc82f5ffd>;
>> +			opp-supported-hw = <0x1f>;
>> +		};
>> +	};
>> +
>>  };
>>  
>>  &gpucc {
>> @@ -41,6 +150,13 @@ &pcie6a_phy {
>>  	compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy";
>>  };
>>  
>> +&qfprom {
>> +	gpu_speed_bin: gpu_speed_bin@119 {
> 
> No underscores. You need to align downstream code to upstream. See
> coding style.

Ack.

-Akhil

> 
> 
> 
> Best regards,
> Krzysztof

Re: [PATCH v2 0/4] Support for Adreno X1-45 GPU

[Jens Glathe]

On 6/11/25 13:15, Akhil P Oommen wrote:

> Add support for X1-45 GPU found in X1P41200 chipset (8 cpu core
> version). X1-45 is a smaller version of X1-85 with lower core count and
> smaller memories. From UMD perspective, this is similar to "FD735"
> present in Mesa.
>
Hi Akhil,

when loading the driver (still without firmware files) I'm getting a 
speedbin warning:

[    3.318341] adreno 3d00000.gpu: [drm:a6xx_gpu_init [msm]] *ERROR* 
missing support for speed-bin: 233. Some OPPs may not be supported by 
hardware

I've seen that there is a table for speed bins, this one is not there. 
Tested on a Lenovo ThinkBook 16 G7 QOY.

with best regards

Jens

Re: [PATCH v2 0/4] Support for Adreno X1-45 GPU

[Akhil P Oommen]

On 6/12/2025 5:32 PM, Jens Glathe wrote:
> On 6/11/25 13:15, Akhil P Oommen wrote:
> 
>> Add support for X1-45 GPU found in X1P41200 chipset (8 cpu core
>> version). X1-45 is a smaller version of X1-85 with lower core count and
>> smaller memories. From UMD perspective, this is similar to "FD735"
>> present in Mesa.
>>
> Hi Akhil,
> 
> when loading the driver (still without firmware files) I'm getting a
> speedbin warning:
> 
> [    3.318341] adreno 3d00000.gpu: [drm:a6xx_gpu_init [msm]] *ERROR*
> missing support for speed-bin: 233. Some OPPs may not be supported by
> hardware
> 
> I've seen that there is a table for speed bins, this one is not there.
> Tested on a Lenovo ThinkBook 16 G7 QOY.

Hi Jens,

Could you please try the below patch?

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 2db748ce7df5..7748f92919b8 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -1510,7 +1510,8 @@ static const struct adreno_info a7xx_gpus[] = {
                        { 0,   0 },
                        { 294, 1 },
                        { 263, 2 },
-                       { 141, 3 },
+                       { 233, 3 },
+                       { 141, 4 },
                ),
        }
 };

With this, you should see 1107Mhz as the GPU Fmax.

-Akhil.

> 
> with best regards
> 
> Jens
> 

Re: [PATCH v2 0/4] Support for Adreno X1-45 GPU

[Konrad Dybcio]

On 6/12/25 11:19 PM, Akhil P Oommen wrote:
> On 6/12/2025 5:32 PM, Jens Glathe wrote:
>> On 6/11/25 13:15, Akhil P Oommen wrote:
>>
>>> Add support for X1-45 GPU found in X1P41200 chipset (8 cpu core
>>> version). X1-45 is a smaller version of X1-85 with lower core count and
>>> smaller memories. From UMD perspective, this is similar to "FD735"
>>> present in Mesa.
>>>
>> Hi Akhil,
>>
>> when loading the driver (still without firmware files) I'm getting a
>> speedbin warning:
>>
>> [    3.318341] adreno 3d00000.gpu: [drm:a6xx_gpu_init [msm]] *ERROR*
>> missing support for speed-bin: 233. Some OPPs may not be supported by
>> hardware
>>
>> I've seen that there is a table for speed bins, this one is not there.
>> Tested on a Lenovo ThinkBook 16 G7 QOY.
> 
> Hi Jens,
> 
> Could you please try the below patch?
> 
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> index 2db748ce7df5..7748f92919b8 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> @@ -1510,7 +1510,8 @@ static const struct adreno_info a7xx_gpus[] = {
>                         { 0,   0 },
>                         { 294, 1 },
>                         { 263, 2 },
> -                       { 141, 3 },
> +                       { 233, 3 },
> +                       { 141, 4 },
>                 ),
>         }
>  };
> 
> With this, you should see 1107Mhz as the GPU Fmax.

I see your dt entry takes care of bins 0..=4.. this oversight worries
me a bit - are these values above (post change) all in sync with what
you entered into DT?

I'm not saying they necessarily aren't, but I want to avoid
inconsistencies

Konrad

Re: [PATCH v2 0/4] Support for Adreno X1-45 GPU

[Akhil P Oommen]

On 6/15/2025 12:12 AM, Konrad Dybcio wrote:
> On 6/12/25 11:19 PM, Akhil P Oommen wrote:
>> On 6/12/2025 5:32 PM, Jens Glathe wrote:
>>> On 6/11/25 13:15, Akhil P Oommen wrote:
>>>
>>>> Add support for X1-45 GPU found in X1P41200 chipset (8 cpu core
>>>> version). X1-45 is a smaller version of X1-85 with lower core count and
>>>> smaller memories. From UMD perspective, this is similar to "FD735"
>>>> present in Mesa.
>>>>
>>> Hi Akhil,
>>>
>>> when loading the driver (still without firmware files) I'm getting a
>>> speedbin warning:
>>>
>>> [    3.318341] adreno 3d00000.gpu: [drm:a6xx_gpu_init [msm]] *ERROR*
>>> missing support for speed-bin: 233. Some OPPs may not be supported by
>>> hardware
>>>
>>> I've seen that there is a table for speed bins, this one is not there.
>>> Tested on a Lenovo ThinkBook 16 G7 QOY.
>>
>> Hi Jens,
>>
>> Could you please try the below patch?
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> index 2db748ce7df5..7748f92919b8 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> @@ -1510,7 +1510,8 @@ static const struct adreno_info a7xx_gpus[] = {
>>                         { 0,   0 },
>>                         { 294, 1 },
>>                         { 263, 2 },
>> -                       { 141, 3 },
>> +                       { 233, 3 },
>> +                       { 141, 4 },
>>                 ),
>>         }
>>  };
>>
>> With this, you should see 1107Mhz as the GPU Fmax.
> 
> I see your dt entry takes care of bins 0..=4.. this oversight worries
> me a bit - are these values above (post change) all in sync with what
> you entered into DT?

Yes. DT is accurate. And with this additional change both the driver and
DT will be consistent.

-Akhil.

> 
> I'm not saying they necessarily aren't, but I want to avoid
> inconsistencies
> 
> Konrad
> 

Re: [PATCH v2 0/4] Support for Adreno X1-45 GPU

[Jens Glathe]

On 12.06.25 23:19, Akhil P Oommen wrote:
> Hi Jens,
>
> Could you please try the below patch?
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> index 2db748ce7df5..7748f92919b8 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
> @@ -1510,7 +1510,8 @@ static const struct adreno_info a7xx_gpus[] = {
>                          { 0,   0 },
>                          { 294, 1 },
>                          { 263, 2 },
> -                       { 141, 3 },
> +                       { 233, 3 },
> +                       { 141, 4 },
>                  ),
>          }
>   };
>
> With this, you should see 1107Mhz as the GPU Fmax.
>
jglathe@tb16-jg:~$ cat /sys/class/devfreq/*gpu*/available_frequencies
280000000 380000000 550000000 666000000 720000000 825000000 940000000 
1014000000 1107000000

Looking good. Thanks!

Tested-by: Jens Glathe <jens.glathe@oldschoolsolutions.biz>

with best regards

Jens