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Tue, 26 Aug 2025 21:32:29 -0700 (PDT) Received: from [127.0.0.1] ([5.248.55.4]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-61c78e49ca4sm4263216a12.47.2025.08.26.21.32.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 26 Aug 2025 21:32:29 -0700 (PDT) Date: Wed, 27 Aug 2025 07:32:27 +0300 From: Svyatoslav To: Mikko Perttunen , Thierry Reding , Thierry Reding , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mauro Carvalho Chehab , Greg Kroah-Hartman , Dmitry Osipenko , Charan Pedumuru CC: linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Subject: =?US-ASCII?Q?Re=3A_=5BPATCH_v1_01/19=5D_clk=3A_tegra=3A_ini?= =?US-ASCII?Q?t_CSUS_clock_for_Tegra20_and_Tegra30?= User-Agent: K-9 Mail for Android In-Reply-To: <1909286.atdPhlSkOF@senjougahara> References: <20250819121631.84280-1-clamor95@gmail.com> <20250819121631.84280-2-clamor95@gmail.com> <1909286.atdPhlSkOF@senjougahara> Message-ID: <76B1EB6D-B149-43C2-AA56-A15C9DCCA3AF@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" 27 =D1=81=D0=B5=D1=80=D0=BF=D0=BD=D1=8F 2025=E2=80=AF=D1=80=2E 07:09:45 GM= T+03:00, Mikko Perttunen =D0=BF=D0=B8=D1=88=D0=B5= : >On Tuesday, August 19, 2025 9:16=E2=80=AFPM Svyatoslav Ryhel wrote: >> CSUS clock is required to be enabled on camera device configuration or >> else camera module refuses to initiate properly=2E >>=20 >> Signed-off-by: Svyatoslav Ryhel >> --- >> drivers/clk/tegra/clk-tegra20=2Ec | 1 + >> drivers/clk/tegra/clk-tegra30=2Ec | 1 + >> 2 files changed, 2 insertions(+) >>=20 >> diff --git a/drivers/clk/tegra/clk-tegra20=2Ec >> b/drivers/clk/tegra/clk-tegra20=2Ec index 551ef0cf0c9a=2E=2E42f8150c611= 0 100644 >> --- a/drivers/clk/tegra/clk-tegra20=2Ec >> +++ b/drivers/clk/tegra/clk-tegra20=2Ec >> @@ -1043,6 +1043,7 @@ static struct tegra_clk_init_table init_table[] = =3D { >> { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 }, >> { TEGRA20_CLK_VDE, TEGRA20_CLK_PLL_C, 300000000, 0 }, >> { TEGRA20_CLK_PWM, TEGRA20_CLK_PLL_P, 48000000, 0 }, >> + { TEGRA20_CLK_CSUS, TEGRA20_CLK_CLK_MAX, 6000000, 1 }, >> /* must be the last entry */ >> { TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 }, >> }; >> diff --git a/drivers/clk/tegra/clk-tegra30=2Ec >> b/drivers/clk/tegra/clk-tegra30=2Ec index 82a8cb9545eb=2E=2E70e85e2949e= 0 100644 >> --- a/drivers/clk/tegra/clk-tegra30=2Ec >> +++ b/drivers/clk/tegra/clk-tegra30=2Ec >> @@ -1237,6 +1237,7 @@ static struct tegra_clk_init_table init_table[] = =3D { >> { TEGRA30_CLK_HDA, TEGRA30_CLK_PLL_P, 102000000, 0 }, >> { TEGRA30_CLK_HDA2CODEC_2X, TEGRA30_CLK_PLL_P, 48000000, 0 }, >> { TEGRA30_CLK_PWM, TEGRA30_CLK_PLL_P, 48000000, 0 }, >> + { TEGRA30_CLK_CSUS, TEGRA30_CLK_CLK_MAX, 6000000, 1 }, >> /* must be the last entry */ >> { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 }, >> }; > >I looked into what this clock does and it seems to be a gate for the CSUS= pin,=20 >which provides an output clock for camera sensors (VI MCLK)=2E Default so= urce=20 >seems to be PLLC_OUT1=2E It would be good to note that on the commit mess= age, as=20 >I can't find any documentation about the CSUS clock elsewhere=2E > >What is the 6MHz rate based on? > 6mhz is the statistic value which I was not able to alter while testing=2E= I have tried 12mhz and 24mhz too but it remained 6mhz, so I left it 6mhz= =2E >Since this seems to be a clock consumed by the sensor, it seems to me tha= t=20 >rather than making it always on, we could point to it in the sensor's dev= ice=20 >tree entry=2E > Sensor device tree uses vi_sensor as clocks source and sensor drivers don'= t support multiple linked clocks=2E >Cheers, >Mikko > > >