Re: [PATCH 4/5] drm/msm: Pass mmu features to generic layers

[Vivek Gautam <vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>]

Hi Sharat,


On 3/23/2018 12:49 PM, Sharat Masetty wrote:
> Allow different Adreno targets the ability to pass
> specific mmu features to the generic layers. This will
> help conditionally configure certain iommu features for
> certain Adreno targets.
>
> Also Add a few simple support functions to support a bitmask of
> features that a specific MMU implementation supports.
>
> Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>

Just a nit; please see my comment below.

> ---
>   drivers/gpu/drm/msm/adreno/a3xx_gpu.c   |  2 +-
>   drivers/gpu/drm/msm/adreno/a4xx_gpu.c   |  2 +-
>   drivers/gpu/drm/msm/adreno/a5xx_gpu.c   |  2 +-
>   drivers/gpu/drm/msm/adreno/a6xx_gpu.c   |  2 +-
>   drivers/gpu/drm/msm/adreno/adreno_gpu.c |  4 +++-
>   drivers/gpu/drm/msm/adreno/adreno_gpu.h |  2 +-
>   drivers/gpu/drm/msm/msm_gpu.c           |  6 ++++--
>   drivers/gpu/drm/msm/msm_gpu.h           |  1 +
>   drivers/gpu/drm/msm/msm_mmu.h           | 13 +++++++++++++
>   9 files changed, 26 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
> index 1dd84d3..a7a8573 100644
> --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
> @@ -492,7 +492,7 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
>   	adreno_gpu->registers = a3xx_registers;
>   	adreno_gpu->reg_offsets = a3xx_register_offsets;
>   
> -	ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
> +	ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1, 0);
>   	if (ret)
>   		goto fail;
>   
> diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
> index 2884b1b..5e7e15d6 100644
> --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
> @@ -574,7 +574,7 @@ struct msm_gpu *a4xx_gpu_init(struct drm_device *dev)
>   	adreno_gpu->registers = a4xx_registers;
>   	adreno_gpu->reg_offsets = a4xx_register_offsets;
>   
> -	ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
> +	ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1, 0);
>   	if (ret)
>   		goto fail;
>   
> diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> index a4f68af..c9e06ff 100644
> --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
> @@ -1295,7 +1295,7 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev)
>   
>   	check_speed_bin(&pdev->dev);
>   
> -	ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 4);
> +	ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 4, 0);
>   	if (ret) {
>   		a5xx_destroy(&(a5xx_gpu->base.base));
>   		return ERR_PTR(ret);
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index e83b066..bd50674 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -1040,7 +1040,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
>   	adreno_gpu->registers = a6xx_registers;
>   	adreno_gpu->reg_offsets = a6xx_register_offsets;
>   
> -	ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 4);
> +	ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 4, 0);
>   	if (ret) {
>   		a6xx_destroy(&(a6xx_gpu->base.base));
>   		return ERR_PTR(ret);
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> index 6657461..a87ec6b 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c
> @@ -557,7 +557,8 @@ static int adreno_get_pwrlevels(struct device *dev,
>   
>   int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
>   		struct adreno_gpu *adreno_gpu,
> -		const struct adreno_gpu_funcs *funcs, int nr_rings)
> +		const struct adreno_gpu_funcs *funcs, int nr_rings,
> +		unsigned long mmu_features)
>   {
>   	struct adreno_platform_config *config = pdev->dev.platform_data;
>   	struct msm_gpu_config adreno_gpu_config  = { 0 };
> @@ -576,6 +577,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
>   	adreno_gpu_config.va_end = 0xffffffff;
>   
>   	adreno_gpu_config.nr_rings = nr_rings;
> +	adreno_gpu_config.mmu_features = mmu_features;
>   
>   	adreno_get_pwrlevels(&pdev->dev, gpu);
>   
> diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> index bb9affd..19eda65 100644
> --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
> @@ -225,7 +225,7 @@ void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
>   
>   int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
>   		struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
> -		int nr_rings);
> +		int nr_rings, unsigned long mmu_features);
>   void adreno_gpu_cleanup(struct adreno_gpu *gpu);
>   int adreno_load_fw(struct adreno_gpu *adreno_gpu);
>   
> diff --git a/drivers/gpu/drm/msm/msm_gpu.c b/drivers/gpu/drm/msm/msm_gpu.c
> index ce8e781..c7f616c 100644
> --- a/drivers/gpu/drm/msm/msm_gpu.c
> +++ b/drivers/gpu/drm/msm/msm_gpu.c
> @@ -704,7 +704,7 @@ static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu)
>   
>   static struct msm_gem_address_space *
>   msm_gpu_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev,
> -		uint64_t va_start, uint64_t va_end)
> +		uint64_t va_start, uint64_t va_end, unsigned long mmu_features)
>   {
>   	struct iommu_domain *iommu;
>   	struct msm_gem_address_space *aspace;
> @@ -732,6 +732,8 @@ static int get_clocks(struct platform_device *pdev, struct msm_gpu *gpu)
>   		return ERR_CAST(aspace);
>   	}
>   
> +	msm_mmu_set_feature(aspace->mmu, mmu_features);
> +
>   	ret = aspace->mmu->funcs->attach(aspace->mmu, NULL, 0);
>   	if (ret) {
>   		msm_gem_address_space_put(aspace);
> @@ -815,7 +817,7 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
>   	msm_devfreq_init(gpu);
>   
>   	gpu->aspace = msm_gpu_create_address_space(gpu, pdev,
> -		config->va_start, config->va_end);
> +		config->va_start, config->va_end, config->mmu_features);
>   
>   	if (gpu->aspace == NULL)
>   		dev_info(drm->dev, "%s: no IOMMU, fallback to VRAM carveout!\n", name);
> diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
> index 96058d2..dff9973 100644
> --- a/drivers/gpu/drm/msm/msm_gpu.h
> +++ b/drivers/gpu/drm/msm/msm_gpu.h
> @@ -34,6 +34,7 @@ struct msm_gpu_config {
>   	uint64_t va_start;
>   	uint64_t va_end;
>   	unsigned int nr_rings;
> +	unsigned long mmu_features;
>   };
>   
>   /* So far, with hardware that I've seen to date, we can have:
> diff --git a/drivers/gpu/drm/msm/msm_mmu.h b/drivers/gpu/drm/msm/msm_mmu.h
> index aa2c5d4..85df78d 100644
> --- a/drivers/gpu/drm/msm/msm_mmu.h
> +++ b/drivers/gpu/drm/msm/msm_mmu.h
> @@ -35,6 +35,7 @@ struct msm_mmu {
>   	struct device *dev;
>   	int (*handler)(void *arg, unsigned long iova, int flags);
>   	void *arg;
> +	unsigned long features;
Why do you need a long here? I guess 'int' should suffice.

Best regards
Vivek

>   };
>   
>   static inline void msm_mmu_init(struct msm_mmu *mmu, struct device *dev,
> @@ -54,4 +55,16 @@ static inline void msm_mmu_set_fault_handler(struct msm_mmu *mmu, void *arg,
>   	mmu->handler = handler;
>   }
>   
> +static inline void msm_mmu_set_feature(struct msm_mmu *mmu,
> +		unsigned long feature)
> +{
> +	mmu->features |= feature;
> +}
> +
> +static inline bool msm_mmu_has_feature(struct msm_mmu *mmu,
> +		unsigned long feature)
> +{
> +	return (mmu->features & feature) ? true : false;
> +}
> +
>   #endif /* __MSM_MMU_H__ */

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