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From: Jani Nikula <jani.nikula@linux.intel.com>
To: liuhaoran <liuhaoran14@163.com>, airlied@gmail.com
Cc: intel-gfx@lists.freedesktop.org, liuhaoran <liuhaoran14@163.com>,
	dri-devel@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915/gt: Add error handling in intel_timeline_pin()
Date: Mon, 25 Sep 2023 15:26:54 +0300	[thread overview]
Message-ID: <87o7hqmoa9.fsf@intel.com> (raw)
In-Reply-To: <20230924061632.13665-1-liuhaoran14@163.com>

On Sun, 24 Sep 2023, liuhaoran <liuhaoran14@163.com> wrote:
> This patch adds error-handling for the i915_active_acquire()
> inside the intel_timeline_pin().

Seems to me this is not sufficient.

BR,
Jani.

>
> Signed-off-by: liuhaoran <liuhaoran14@163.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_timeline.c | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_timeline.c b/drivers/gpu/drm/i915/gt/intel_timeline.c
> index b9640212d659..a2edf9233500 100644
> --- a/drivers/gpu/drm/i915/gt/intel_timeline.c
> +++ b/drivers/gpu/drm/i915/gt/intel_timeline.c
> @@ -211,7 +211,11 @@ int intel_timeline_pin(struct intel_timeline *tl, struct i915_gem_ww_ctx *ww)
>  	GT_TRACE(tl->gt, "timeline:%llx using HWSP offset:%x\n",
>  		 tl->fence_context, tl->hwsp_offset);
>  
> -	i915_active_acquire(&tl->active);
> +	err = i915_active_acquire(&tl->active);
> +
> +	if (err)
> +		return err;
> +
>  	if (atomic_fetch_inc(&tl->pin_count)) {
>  		i915_active_release(&tl->active);
>  		__i915_vma_unpin(tl->hwsp_ggtt);

-- 
Jani Nikula, Intel

  reply	other threads:[~2023-09-25 12:27 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-24  6:16 [PATCH] drm/i915/gt: Add error handling in intel_timeline_pin() liuhaoran
2023-09-25 12:26 ` Jani Nikula [this message]
  -- strict thread matches above, loose matches on Subject: below --
2023-09-23 17:35 liuhaoran

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