From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2B6D4C4829A for ; Sun, 11 Feb 2024 15:43:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 947E810E0FE; Sun, 11 Feb 2024 15:43:09 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=oltmanns.dev header.i=@oltmanns.dev header.b="dtbevJw2"; dkim-atps=neutral Received: from mout-p-102.mailbox.org (mout-p-102.mailbox.org [80.241.56.152]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2094A10E0FE for ; Sun, 11 Feb 2024 15:42:58 +0000 (UTC) Received: from smtp1.mailbox.org (smtp1.mailbox.org [IPv6:2001:67c:2050:b231:465::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-p-102.mailbox.org (Postfix) with ESMTPS id 4TXsL23Rdhz9scZ; Sun, 11 Feb 2024 16:42:50 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oltmanns.dev; s=MBO0001; t=1707666170; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=98aDbHgBbGqJamJlcPsF9M6fGfi3Twm9F/GrRpw8fzI=; b=dtbevJw2RvdVTy1+oh5ExI/QO4OF403FR6JiNYzrqWdLydcjnRivDO15lGVH9EtidDlKzl oyXvxHTUS2c4XApjWIuMjMOgBxMKmmmDtrkPpSXmfDot5xPTE1TtEO9iGJfByr0YJa8sT0 FTifdEFNutdUrivRSWb3OFHI/17FqDhzk8iAgTgM/Kq6cQZWiECx2tOPlxJq0xauL8o6/f in9z6b7cL4yVjxXoSxoumh0x9U8qViyV1w2GC0AukoHC0EtFBYyXrGKje/BEMpqVxg6wo2 FoCa5h/xYhFO2TyLCITT9NvnUlOQIuuEBgy3nnNQvBoFXkqUm0Wmo8t4NOo4XQ== References: <20240205-pinephone-pll-fixes-v2-0-96a46a2d8c9b@oltmanns.dev> <20240205-pinephone-pll-fixes-v2-5-96a46a2d8c9b@oltmanns.dev> From: Frank Oltmanns To: Maxime Ripard Cc: Michael Turquette , Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Guido =?utf-8?Q?G=C3=BCnther?= , Purism Kernel Team , Ondrej Jirman , Neil Armstrong , Jessica Zhang , Sam Ravnborg , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org Subject: Re: [PATCH v2 5/6] drm/panel: st7703: Drive XBD599 panel at higher clock rate In-reply-to: Date: Sun, 11 Feb 2024 16:42:43 +0100 Message-ID: <87sf1zxb0s.fsf@oltmanns.dev> MIME-Version: 1.0 Content-Type: text/plain X-Rspamd-Queue-Id: 4TXsL23Rdhz9scZ X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 2024-02-08 at 20:05:08 +0100, Maxime Ripard wrote: > [[PGP Signed Part:Undecided]] > Hi Frank, > > On Mon, Feb 05, 2024 at 04:22:28PM +0100, Frank Oltmanns wrote: >> This panel is used in the pinephone that runs on a Allwinner A64 SOC. >> The SOC requires pll-mipi to run at more than 500 MHz. >> >> This is the relevant clock tree: >> pll-mipi >> tcon0 >> tcon-data-clock >> >> tcon-data-clock has to run at 1/4 the DSI per-lane bit rate. The XBD599 >> has 24 bpp and 4 lanes. Therefore, the resulting requested >> tcon-data-clock rate is: >> crtc_clock * 1000 * (24 / 4) / 4 >> >> tcon-data-clock runs at tcon0 / 4 (fixed divisor), so it requests a >> parent rate of >> 4 * (crtc_clock * 1000 * (24 / 4) / 4) >> >> Since tcon0 is a ccu_mux, the rate of tcon0 equals the rate of pll-mipi. >> >> pll-mipi's constraint to run at 500MHz or higher forces us to have a >> crtc_clock >= 83333 kHz if we want a 60 Hz vertical refresh rate. >> >> Change [hv]sync_(start|end) so that we reach a clock rate of 83502 kHz >> so that it is high enough to align with pll-pipi limits. >> >> Signed-off-by: Frank Oltmanns > > That commit log is great, but it's kind of off-topic. It's a panel > driver, it can be used on any MIPI-DSI controller, the only relevant > information there should be the panel timings required in the datasheet. > > The PLL setup is something for the MIPI-DSI driver to adjust, not for > the panel to care for. > I absolutely agree. It even was the reason for my submission of a sunxi-ng patch series last year that was accepted, to make pll-mipi more flexible. :) The only remaining option I currently see for adjusting the sunxi-ng driver to further accomodate the panel, is trying to use a higher divisor than 4 for calculating tcon-data-clock from tcon0. I remember reading a discussion about this, but as far as I remember that proposal was rejected (by you, IIRC). While I appreciate other suggestion as well, I'll look into options for using a different divisor than 4. Best regards, Frank > > Maxime > > [[End of PGP Signed Part]]