From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E0C96C433EF for ; Fri, 11 Feb 2022 02:26:13 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D542410E9B5; Fri, 11 Feb 2022 02:26:12 +0000 (UTC) Received: from alexa-out.qualcomm.com (alexa-out.qualcomm.com [129.46.98.28]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6E32710E9B5; Fri, 11 Feb 2022 02:26:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1644546371; x=1676082371; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=YcwbUePQCMjnTa3cPwb9sMqUhB8PWHxbGQVUtPcWJNE=; b=DaeUpGqqAOKtqw7cXqysMaEzdE6u0FMqSrXri4HbBq2bd904MxQeH9GT EKvAeMT63YCeGQJN2i0KvPzTceaDbHz7eJ+4aYYPa1n3ieNtRAcXdMxPp BUpnqitKD3o4nJngeVYHlB9n+2EPF4Ed/PdV8Hkecv80zIF4dEmN49kmH U=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 10 Feb 2022 18:26:11 -0800 X-QCInternal: smtphost Received: from nasanex01c.na.qualcomm.com ([10.47.97.222]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Feb 2022 18:26:11 -0800 Received: from nalasex01a.na.qualcomm.com (10.47.209.196) by nasanex01c.na.qualcomm.com (10.47.97.222) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Thu, 10 Feb 2022 18:26:10 -0800 Received: from [10.111.162.111] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.922.19; Thu, 10 Feb 2022 18:26:07 -0800 Message-ID: <8eb63d37-fd3e-e9cc-5249-bc6ed8958cd8@quicinc.com> Date: Thu, 10 Feb 2022 18:26:05 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:91.0) Gecko/20100101 Thunderbird/91.5.1 Subject: Re: [PATCH 2/3] drm/msm/dpu: Update the comment style Content-Language: en-US To: Vinod Koul , Rob Clark References: <20220210114106.290669-1-vkoul@kernel.org> <20220210114106.290669-2-vkoul@kernel.org> From: Abhinav Kumar In-Reply-To: <20220210114106.290669-2-vkoul@kernel.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kalyan Thota , freedreno@lists.freedesktop.org, David Airlie , linux-arm-msm@vger.kernel.org, Kuogee Hsieh , dri-devel@lists.freedesktop.org, Bjorn Andersson , Dmitry Baryshkov , Stephen Boyd , Sean Paul , Guenter Roeck , Mark Yacoub Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 2/10/2022 3:41 AM, Vinod Koul wrote: > The multi line comment style is wrongly used as kernel-doc comment. This > gives a warning: > > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c:17: > warning: This comment starts with '/**', but isn't a kernel-doc comment. > Refer Documentation/doc-guide/kernel-doc.rst > > Update the style to fix this. > > Signed-off-by: Vinod Koul Reviewed-by: Abhinav Kumar > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c > index a77a5eaa78ad..9341c88a336f 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c > @@ -13,7 +13,7 @@ > #include "dpu_hw_mdss.h" > #include "dpu_trace.h" > > -/** > +/* > * Register offsets in MDSS register file for the interrupt registers > * w.r.t. to the MDP base > */