From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 34BD9C43334 for ; Wed, 13 Jul 2022 09:31:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CD2CB98AAF; Wed, 13 Jul 2022 09:31:11 +0000 (UTC) Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by gabe.freedesktop.org (Postfix) with ESMTPS id E7A8E98ABE for ; Wed, 13 Jul 2022 09:31:09 +0000 (UTC) X-UUID: 7c9ab3c345e64b41b9926e33f6bbac94-20220713 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.8, REQID:ca50afd8-b7df-4c67-9166-916496b64597, OB:0, LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:0f94e32, CLOUDID:a3715fd7-5d6d-4eaf-a635-828a3ee48b7c, C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:nil,BEC:nil,COL:0 X-UUID: 7c9ab3c345e64b41b9926e33f6bbac94-20220713 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 568296446; Wed, 13 Jul 2022 17:31:03 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Wed, 13 Jul 2022 17:31:02 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 13 Jul 2022 17:31:02 +0800 Message-ID: <9eceb5412bfed5f408153fe05bc2f8a4e3570b77.camel@mediatek.com> Subject: Re: [PATCH v14 05/10] drm/mediatek: Add MT8195 Embedded DisplayPort driver From: CK Hu To: Bo-Chen Chen , , , , , , , , , , Date: Wed, 13 Jul 2022 17:31:02 +0800 In-Reply-To: <20220712111223.13080-6-rex-bc.chen@mediatek.com> References: <20220712111223.13080-1-rex-bc.chen@mediatek.com> <20220712111223.13080-6-rex-bc.chen@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-fbdev@vger.kernel.org, granquet@baylibre.com, jitao.shi@mediatek.com, liangxu.xu@mediatek.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, msp@baylibre.com, Project_Global_Chrome_Upstream_Group@mediatek.com, linux-mediatek@lists.infradead.org, wenst@chromium.org, linux-arm-kernel@lists.infradead.org, angelogioacchino.delregno@collabora.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi, Bo-Chen: On Tue, 2022-07-12 at 19:12 +0800, Bo-Chen Chen wrote: > From: Markus Schneider-Pargmann > > This patch adds a embedded displayport driver for the MediaTek mt8195 > SoC. > > It supports the MT8195, the embedded DisplayPort units. It offers > DisplayPort 1.4 with up to 4 lanes. > > The driver creates a child device for the phy. The child device will > never exist without the parent being active. As they are sharing a > register range, the parent passes a regmap pointer to the child so > that > both can work with the same register range. The phy driver sets > device > data that is read by the parent to get the phy device that can be > used > to control the phy properties. > > This driver is based on an initial version by > Jitao shi > > Signed-off-by: Markus Schneider-Pargmann > Signed-off-by: Guillaume Ranquet > Signed-off-by: Bo-Chen Chen > --- [snip] > + > +static void mtk_dp_bulk_16bit_write(struct mtk_dp *mtk_dp, u32 > offset, u8 *buf, > + size_t length) The offset would always be MTK_DP_AUX_P0_3708, so drop offset and use MTK_DP_AUX_P0_3708 directly. > +{ > + int i; > + int num_regs = (length + 1) / 2; > + > + /* 2 bytes per register */ > + for (i = 0; i < num_regs; i++) { > + u32 val = buf[i * 2] | > + (i * 2 + 1 < length ? buf[i * 2 + 1] << 8 : > 0); > + > + if (mtk_dp_write(mtk_dp, offset + i * 4, val)) > + return; > + } for (i = 0; i < length; i += 2) { val = buf[i] | (i + 1 < length ? buf[i + 1] << 8 : 0); if (mtk_dp_write(mtk_dp, MTK_DP_AUX_P0_3708 + i * 2, val)) return; } Regards, CK > +} > +