From: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
David Airlie <airlied@gmail.com>,
Simona Vetter <simona@ffwll.ch>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
dri-devel@lists.freedesktop.org,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Fabrizio Castro <fabrizio.castro.jz@renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v5 10/12] drm: renesas: rz-du: mipi_dsi: Add dphy_late_init() callback for RZ/V2H(P)
Date: Wed, 21 May 2025 14:10:24 +0100 [thread overview]
Message-ID: <CA+V-a8sxHiddge_U7SLr6jBdjVvDFCzqsr6mgZBCoyVsjo9Uxg@mail.gmail.com> (raw)
In-Reply-To: <20250520142815.GJ13321@pendragon.ideasonboard.com>
Hi Laurent,
Thank you for the review.
On Tue, May 20, 2025 at 3:28 PM Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
>
> Hi Prabhakar,
>
> Thank you for the patch.
>
> On Mon, May 12, 2025 at 07:23:28PM +0100, Prabhakar wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Introduce the `dphy_late_init` callback in `rzg2l_mipi_dsi_hw_info` to
> > allow additional D-PHY register configurations after enabling data and
> > clock lanes. This is required for the RZ/V2H(P) SoC but not for the
> > RZ/G2L SoC.
> >
> > Modify `rzg2l_mipi_dsi_startup()` to invoke `dphy_late_init` if defined,
> > ensuring SoC-specific initialization is performed only when necessary.
> >
> > This change prepares for RZ/V2H(P) SoC support while maintaining
> > compatibility with existing platforms.
> >
> > Co-developed-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v4->v5:
> > - Added Reviewed tag from Biju
> >
> > v3->v4:
> > - No changes
> >
> > v2->v3:
> > - No changes
> >
> > v1->v2:
> > - No changes
> > ---
> > drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> > index 55a1c1b043c8..e1ce21a9ddb3 100644
> > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> > @@ -34,6 +34,7 @@ struct rzg2l_mipi_dsi;
> >
> > struct rzg2l_mipi_dsi_hw_info {
> > int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, u64 hsfreq_millihz);
> > + void (*dphy_late_init)(struct rzg2l_mipi_dsi *dsi);
>
> As this is called at startup time I would have called it dphy_startup.
> Up to you.
>
Agreed, I will rename this to dphy_startup_late_init().
Cheers,
Prabhakar
> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
>
> > void (*dphy_exit)(struct rzg2l_mipi_dsi *dsi);
> > u32 phy_reg_offset;
> > u32 link_reg_offset;
> > @@ -320,6 +321,9 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi,
> > txsetr = TXSETR_DLEN | TXSETR_NUMLANEUSE(dsi->lanes - 1) | TXSETR_CLEN;
> > rzg2l_mipi_dsi_link_write(dsi, TXSETR, txsetr);
> >
> > + if (dsi->info->dphy_late_init)
> > + dsi->info->dphy_late_init(dsi);
> > +
> > hsfreq = DIV_ROUND_CLOSEST_ULL(hsfreq_millihz, MILLI);
> > /*
> > * Global timings characteristic depends on high speed Clock Frequency
>
> --
> Regards,
>
> Laurent Pinchart
next prev parent reply other threads:[~2025-05-21 13:57 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-12 18:23 [PATCH v5 00/12] Add DU support for RZ/V2H(P) SoC Prabhakar
2025-05-12 18:23 ` [PATCH v5 01/12] dt-bindings: display: renesas, rzg2l-du: Add " Prabhakar
2025-05-20 13:52 ` [PATCH v5 01/12] dt-bindings: display: renesas,rzg2l-du: " Laurent Pinchart
2025-05-12 18:23 ` [PATCH v5 02/12] drm: renesas: rz-du: " Prabhakar
2025-05-20 13:56 ` Laurent Pinchart
2025-05-12 18:23 ` [PATCH v5 03/12] drm: renesas: rz-du: mipi_dsi: Add min check for VCLK range Prabhakar
2025-05-20 13:58 ` Laurent Pinchart
2025-05-21 13:01 ` Lad, Prabhakar
2025-05-12 18:23 ` [PATCH v5 04/12] drm: renesas: rz-du: mipi_dsi: Simplify HSFREQ calculation Prabhakar
2025-05-20 14:05 ` Laurent Pinchart
2025-05-21 13:03 ` Lad, Prabhakar
2025-05-12 18:23 ` [PATCH v5 05/12] drm: renesas: rz-du: mipi_dsi: Use VCLK for " Prabhakar
2025-05-20 14:16 ` Laurent Pinchart
2025-05-21 13:05 ` Lad, Prabhakar
2025-05-21 13:09 ` Biju Das
2025-05-20 14:54 ` Geert Uytterhoeven
2025-05-21 13:06 ` Lad, Prabhakar
2025-05-12 18:23 ` [PATCH v5 06/12] drm: renesas: rz-du: mipi_dsi: Add OF data support Prabhakar
2025-05-20 14:22 ` Laurent Pinchart
2025-05-21 13:08 ` Lad, Prabhakar
2025-05-12 18:23 ` [PATCH v5 07/12] drm: renesas: rz-du: mipi_dsi: Make "rst" reset control optional for RZ/V2H(P) Prabhakar
2025-05-12 19:28 ` Biju Das
2025-05-20 14:26 ` Laurent Pinchart
2025-05-12 18:23 ` [PATCH v5 08/12] drm: renesas: rz-du: mipi_dsi: Use mHz for D-PHY frequency calculations Prabhakar
2025-05-20 14:24 ` Laurent Pinchart
2025-05-21 11:02 ` Fabrizio Castro
2025-05-12 18:23 ` [PATCH v5 09/12] drm: renesas: rz-du: mipi_dsi: Add feature flag for 16BPP support Prabhakar
2025-05-20 14:26 ` Laurent Pinchart
2025-05-12 18:23 ` [PATCH v5 10/12] drm: renesas: rz-du: mipi_dsi: Add dphy_late_init() callback for RZ/V2H(P) Prabhakar
2025-05-20 14:28 ` Laurent Pinchart
2025-05-21 13:10 ` Lad, Prabhakar [this message]
2025-05-12 18:23 ` [PATCH v5 11/12] drm: renesas: rz-du: mipi_dsi: Add function pointers for configuring VCLK and mode validation Prabhakar
2025-05-12 18:23 ` [PATCH v5 12/12] drm: renesas: rz-du: mipi_dsi: Add support for LPCLK clock handling Prabhakar
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