From mboxrd@z Thu Jan 1 00:00:00 1970 From: Oded Gabbay Subject: Re: [PATCH 49/88] drm/amdgpu: remove AMDGPU_GEM_CREATE_CPU_GTT_UC Date: Sat, 06 Jun 2015 17:08:39 +0000 Message-ID: References: <1432696827-3752-1-git-send-email-alexander.deucher@amd.com> <1432696827-3752-19-git-send-email-alexander.deucher@amd.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1272176008==" Return-path: Received: from mail-wi0-f180.google.com (mail-wi0-f180.google.com [209.85.212.180]) by gabe.freedesktop.org (Postfix) with ESMTP id A2A886E1FD for ; Sat, 6 Jun 2015 10:08:51 -0700 (PDT) Received: by wifx6 with SMTP id x6so47623039wif.0 for ; Sat, 06 Jun 2015 10:08:50 -0700 (PDT) In-Reply-To: <1432696827-3752-19-git-send-email-alexander.deucher@amd.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Alex Deucher , dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org --===============1272176008== Content-Type: multipart/alternative; boundary=bcaec55550306cfb3d0517dc76dc --bcaec55550306cfb3d0517dc76dc Content-Type: text/plain; charset=UTF-8 Hi Alex, I think you have a mistake in this patch. You renamed AMDGPU_GEM_CREATE_CPU_GTT_WC to AMDGPU_GEM_CREATE_CPU_GTT_USWC, however, AMDGPU_GEM_CREATE_CPU_GTT_WC was defined as (1 << 3) and AMDGPU_GEM_CREATE_CPU_GTT_USWC is defined as (1 << 2) Oded On Wed, May 27, 2015 at 6:22 AM Alex Deucher wrote: > From: Jammy Zhou > > This flag isn't used by user mode drivers, remove it to avoid > confusion. And rename GTT_WC to GTT_USWC to make it clear. > > Signed-off-by: Jammy Zhou > Reviewed-by: Alex Deucher > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 10 ++-------- > include/uapi/drm/amdgpu_drm.h | 7 ++----- > 2 files changed, 4 insertions(+), 13 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c > b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c > index f5e17f9..992b7f5 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c > @@ -132,10 +132,7 @@ void amdgpu_ttm_placement_from_domain(struct > amdgpu_bo *rbo, u32 domain) > } > > if (domain & AMDGPU_GEM_DOMAIN_GTT) { > - if (rbo->flags & AMDGPU_GEM_CREATE_CPU_GTT_UC) { > - rbo->placements[c].fpfn = 0; > - rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED > | TTM_PL_FLAG_TT; > - } else if (rbo->flags & AMDGPU_GEM_CREATE_CPU_GTT_WC) { > + if (rbo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) { > rbo->placements[c].fpfn = 0; > rbo->placements[c++].flags = TTM_PL_FLAG_WC | > TTM_PL_FLAG_TT | > > TTM_PL_FLAG_UNCACHED; > @@ -146,10 +143,7 @@ void amdgpu_ttm_placement_from_domain(struct > amdgpu_bo *rbo, u32 domain) > } > > if (domain & AMDGPU_GEM_DOMAIN_CPU) { > - if (rbo->flags & AMDGPU_GEM_CREATE_CPU_GTT_UC) { > - rbo->placements[c].fpfn = 0; > - rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED > | TTM_PL_FLAG_SYSTEM; > - } else if (rbo->flags & AMDGPU_GEM_CREATE_CPU_GTT_WC) { > + if (rbo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) { > rbo->placements[c].fpfn = 0; > rbo->placements[c++].flags = TTM_PL_FLAG_WC | > TTM_PL_FLAG_SYSTEM | > > TTM_PL_FLAG_UNCACHED; > diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h > index 9e771fb..77bc574 100644 > --- a/include/uapi/drm/amdgpu_drm.h > +++ b/include/uapi/drm/amdgpu_drm.h > @@ -73,15 +73,12 @@ > #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) > /* Flag that CPU access will not work, this VRAM domain is invisible */ > #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) > -/* Flag that un-cached attributes should be used for GTT */ > -#define AMDGPU_GEM_CREATE_CPU_GTT_UC (1 << 2) > /* Flag that USWC attributes should be used for GTT */ > -#define AMDGPU_GEM_CREATE_CPU_GTT_WC (1 << 3) > +#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) > > /* Flag mask for GTT domain_flags */ > #define AMDGPU_GEM_CREATE_CPU_GTT_MASK \ > - (AMDGPU_GEM_CREATE_CPU_GTT_WC | \ > - AMDGPU_GEM_CREATE_CPU_GTT_UC | \ > + (AMDGPU_GEM_CREATE_CPU_GTT_USWC | \ > AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | \ > AMDGPU_GEM_CREATE_NO_CPU_ACCESS) > > -- > 1.8.3.1 > > _______________________________________________ > dri-devel mailing list > dri-devel@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/dri-devel > --bcaec55550306cfb3d0517dc76dc Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable
Hi Alex,
I think you have a mistake in this patch.
= You renamed=C2=A0AMDGPU_GEM_CREATE_CPU_GTT_WC to=C2=A0AMDGPU_GEM= _CREATE_CPU_GTT_USWC, however,=C2=A0AMDGPU_GEM_CREATE_CPU_G= TT_WC was defined as (1 << 3) and=C2=A0AMDGPU_GEM_CREATE_CPU_= GTT_USWC is defined as (1 << 2)

Oded

On Wed, May 27, 2015 at 6:22 AM Alex Deucher <alexdeucher@gmail.com> wrote:
From: Jammy Zhou <Jammy.Zhou@amd.com>

This flag isn't used by user mode drivers, remove it to avoid
confusion. And rename GTT_WC to GTT_USWC to make it clear.

Signed-off-by: Jammy Zhou <Jammy.Zhou@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
---
=C2=A0drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 10 ++--------
=C2=A0include/uapi/drm/amdgpu_drm.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 |=C2=A0 7 ++-----
=C2=A02 files changed, 4 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/a= md/amdgpu/amdgpu_object.c
index f5e17f9..992b7f5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -132,10 +132,7 @@ void amdgpu_ttm_placement_from_domain(struct amdgpu_bo= *rbo, u32 domain)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 }

=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (domain & AMDGPU_GEM_DOMAIN_GTT) {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (rbo->flags &= amp; AMDGPU_GEM_CREATE_CPU_GTT_UC) {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0rbo->placements[c].fpfn =3D 0;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0rbo->placements[c++].flags =3D TTM_PL_FLAG_UNCACHED | TTM_PL_F= LAG_TT;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0} else if (rbo->= flags & AMDGPU_GEM_CREATE_CPU_GTT_WC) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (rbo->flags &= amp; AMDGPU_GEM_CREATE_CPU_GTT_USWC) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 rbo->placements[c].fpfn =3D 0;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 rbo->placements[c++].flags =3D TTM_PL_FLAG_WC | TTM_PL_FLAG_T= T |
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0TTM_PL_FL= AG_UNCACHED;
@@ -146,10 +143,7 @@ void amdgpu_ttm_placement_from_domain(struct amdgpu_bo= *rbo, u32 domain)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 }

=C2=A0 =C2=A0 =C2=A0 =C2=A0 if (domain & AMDGPU_GEM_DOMAIN_CPU) {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (rbo->flags &= amp; AMDGPU_GEM_CREATE_CPU_GTT_UC) {
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0rbo->placements[c].fpfn =3D 0;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0rbo->placements[c++].flags =3D=C2=A0 TTM_PL_FLAG_UNCACHED | TT= M_PL_FLAG_SYSTEM;
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0} else if (rbo->= flags & AMDGPU_GEM_CREATE_CPU_GTT_WC) {
+=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0if (rbo->flags &= amp; AMDGPU_GEM_CREATE_CPU_GTT_USWC) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 rbo->placements[c].fpfn =3D 0;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 rbo->placements[c++].flags =3D TTM_PL_FLAG_WC | TTM_PL_FLAG_S= YSTEM |
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0TTM_PL_FL= AG_UNCACHED;
diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h<= br> index 9e771fb..77bc574 100644
--- a/include/uapi/drm/amdgpu_drm.h
+++ b/include/uapi/drm/amdgpu_drm.h
@@ -73,15 +73,12 @@
=C2=A0#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED=C2=A0 (1 << 0) =C2=A0/* Flag that CPU access will not work, this VRAM domain is invisible = */
=C2=A0#define AMDGPU_GEM_CREATE_NO_CPU_ACCESS=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 (1 << 1)
-/* Flag that un-cached attributes should be used for GTT */
-#define AMDGPU_GEM_CREATE_CPU_GTT_UC=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0(1 << 2)
=C2=A0/* Flag that USWC attributes should be used for GTT */
-#define AMDGPU_GEM_CREATE_CPU_GTT_WC=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0(1 << 3)
+#define AMDGPU_GEM_CREATE_CPU_GTT_USWC=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0(1= << 2)

=C2=A0/* Flag mask for GTT domain_flags */
=C2=A0#define AMDGPU_GEM_CREATE_CPU_GTT_MASK \
-=C2=A0 =C2=A0 =C2=A0 =C2=A0(AMDGPU_GEM_CREATE_CPU_GTT_WC | \
-=C2=A0 =C2=A0 =C2=A0 =C2=A0 AMDGPU_GEM_CREATE_CPU_GTT_UC | \
+=C2=A0 =C2=A0 =C2=A0 =C2=A0(AMDGPU_GEM_CREATE_CPU_GTT_USWC | \
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | \=
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0AMDGPU_GEM_CREATE_NO_CPU_ACCESS)

--
1.8.3.1

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