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[209.85.221.180]) by smtp.gmail.com with ESMTPSA id a1e0cc1a2514c-890277bea3esm2281741241.3.2025.08.19.03.40.45 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 19 Aug 2025 03:40:46 -0700 (PDT) Received: by mail-vk1-f180.google.com with SMTP id 71dfb90a1353d-53b1738e8e3so3841822e0c.1 for ; Tue, 19 Aug 2025 03:40:45 -0700 (PDT) X-Forwarded-Encrypted: i=1; AJvYcCV99hDY5Np2Z0dW7H/Pm83JbXoufYUbJzaZuO1GkdYhYQ21IvqOlXnX8KRsv7iUWqh9RY3Ucf9ocRg=@lists.freedesktop.org X-Received: by 2002:a05:6102:548a:b0:4e6:f7e9:c4a5 with SMTP id ada2fe7eead31-51924b3b1c1mr573466137.22.1755600045268; Tue, 19 Aug 2025 03:40:45 -0700 (PDT) MIME-Version: 1.0 References: <20250728201435.3505594-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20250728201435.3505594-5-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: From: Geert Uytterhoeven Date: Tue, 19 Aug 2025 12:40:34 +0200 X-Gmail-Original-Message-ID: X-Gm-Features: Ac12FXz7ywVTeSgdEqc13iyHS6v2zZGzk_1Dft3Db5rZ3MNDTn1vQslXfUK25bs Message-ID: Subject: Re: [PATCH v7 4/6] dt-bindings: display: bridge: renesas,dsi: Document RZ/V2H(P) and RZ/V2N To: "Lad, Prabhakar" Cc: Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Biju Das , Magnus Damm , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Fabrizio Castro , Tommaso Merciai , Lad Prabhakar , Krzysztof Kozlowski Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Mon, 28 Jul 2025 at 22:28, Lad, Prabhakar w= rote: > On Mon, Jul 28, 2025 at 9:14=E2=80=AFPM Prabhakar wrote: > > From: Lad Prabhakar > > > > Add the compatible string "renesas,r9a09g057-mipi-dsi" for the Renesas > > RZ/V2H(P) (R9A09G057) SoC. While the MIPI DSI LINK registers are shared > > with the RZ/G2L SoC, the D-PHY register layout differs. Additionally, t= he > > RZ/V2H(P) uses only two resets compared to three on RZ/G2L, and require= s > > five clocks instead of six. > > > > To reflect these hardware differences, update the binding schema to > > support the reduced clock and reset requirements for RZ/V2H(P). > > > > Since the RZ/V2N (R9A09G056) SoC integrates an identical DSI IP to > > RZ/V2H(P), the same "renesas,r9a09g057-mipi-dsi" compatible string is > > reused for RZ/V2N. > > > > Signed-off-by: Lad Prabhakar > > Reviewed-by: Krzysztof Kozlowski > > Reviewed-by: Geert Uytterhoeven > > --- > > v6->v7: > > - Renamed pllclk to pllrefclk > > - Preserved the reviewed by tag from Geert and Krzysztof > > > - Included support for RZ/V2N in the same patch > - Updated commit description. > > I missed mentioning the above. Reviewed-by: Geert Uytterhoeven Gr{oetje,eeting}s, Geert --=20 Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k= .org In personal conversations with technical people, I call myself a hacker. Bu= t when I'm talking to journalists I just say "programmer" or something like t= hat. -- Linus Torvalds