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From: "Christopher Snowhill" To: "Tobias Jakobi" , , , References: In-Reply-To: X-Migadu-Flow: FLOW_OUT X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Sun Sep 8, 2024 at 4:23 AM PDT, Tobias Jakobi wrote: > On 9/8/24 09:35, Christopher Snowhill wrote: > > > On Mon Sep 2, 2024 at 2:40 AM PDT, tjakobi wrote: > >> From: Tobias Jakobi > >> > >> Hello, > >> > >> this fixes a nasty race condition in the set_drr() callbacks for DCN10 > >> and DCN35 that has existed now since quite some time, see this GitLab > >> issue for reference. > >> > >> https://gitlab.freedesktop.org/drm/amd/-/issues/3142 > >> > >> The report just focuses von DCN10, but the same problem also exists in > >> the DCN35 code. > > Does the problem not exist in the following references to funcs->set_dr= r? > > > > drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c: if (pip= e_ctx->stream_res.tg->funcs->set_drr) > > drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c: = pipe_ctx->stream_res.tg->funcs->set_drr( > > drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c: = pipe_ctx[i]->stream_res.tg->funcs->set_drr( > > drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c: if (pip= e_ctx->stream_res.tg->funcs->set_drr) > > drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c: = pipe_ctx->stream_res.tg->funcs->set_drr( > > drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c: = if (pipe_ctx->stream_res.tg->funcs->set_drr) > > drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c: = pipe_ctx->stream_res.tg->funcs->set_drr( > > drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c: if (pip= e_ctx->stream_res.tg->funcs->set_drr) > > drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c: = pipe_ctx->stream_res.tg->funcs->set_drr( > > drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c: if (pip= e_ctx->stream_res.tg->funcs->set_drr) > > drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c: = pipe_ctx->stream_res.tg->funcs->set_drr( > > Maybe. But the big difference I see here, is that in this code there=20 > isn't even any kind of NULL check applied to tg. Or most of the members= =20 > of *pipe_ctx. If there really is the same kind of problem here, then one= =20 > would need to rewrite a bit more code to fix stuff. > > E.g. in the case of=C2=A0 dcn31_hwseq.c, the questionable code is in=20 > dcn31_reset_back_end_for_pipe(), which is static and only called from=20 > dcn31_reset_hw_ctx_wrap(). Which is assigned to the .reset_hw_ctx_wrap=20 > callback. And this specific callback, from what I can see, is only=20 > called from dce110_reset_hw_ctx_wrap(). Which is then assigned to the=20 > .apply_ctx_to_hw callback. The callback is only called from=20 > dc_commit_state_no_check(). That one is static again, and called from=20 > dc_commit_streams(). > > I could trace this even further. My point is: I don't think this is=20 > called from any IRQ handler code. And given the depth and complexity of= =20 > the callgraph, I have to admit, that, at least at this point, this is a= =20 > bit over my head. > > Sure, I could now sprinkle a bunch of x !=3D NULL in the code, but that= =20 > would be merely voodoo. And I usually try to have a theoretical basis=20 > when I apply changes to code. > > Maybe if someone from the AMD display team could give some insight if=20 > there still is potentially vulnerable code in some of the instances that= =20 > Christopher has posted, then I would gladly take a look. Sorry, I was taking a note from someone else who mentioned set_drr function= s, and wasn't aware that none of the other implementations happen to be cal= led from IRQ handlers. Thanks for looking into this. -Christopher > With best wishes, > Tobias > > > > >> With best wishes, > >> Tobias > >> > >> Tobias Jakobi (2): > >> drm/amd/display: Avoid race between dcn10_set_drr() and > >> dc_state_destruct() > >> drm/amd/display: Avoid race between dcn35_set_drr() and > >> dc_state_destruct() > >> > >> .../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 20 +++++++++++------= -- > >> .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 20 +++++++++++------= -- > >> 2 files changed, 24 insertions(+), 16 deletions(-)