From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4EE74FED2F1 for ; Thu, 12 Mar 2026 08:47:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A9B8E10E9C0; Thu, 12 Mar 2026 08:47:51 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=kernel.org header.i=@kernel.org header.b="uMNp1T2o"; dkim-atps=neutral Received: from tor.source.kernel.org (tor.source.kernel.org [172.105.4.254]) by gabe.freedesktop.org (Postfix) with ESMTPS id 48FC310E9C0 for ; Thu, 12 Mar 2026 08:47:50 +0000 (UTC) Received: from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58]) by tor.source.kernel.org (Postfix) with ESMTP id 7468B60054; Thu, 12 Mar 2026 08:47:49 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C8C65C4CEF7; Thu, 12 Mar 2026 08:47:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773305269; bh=7k4MK2cTPOusvOGJTfL2Ggrg44rLa75R7DTahSV9x0E=; h=Date:Subject:From:To:References:In-Reply-To:From; b=uMNp1T2oA8TJalV79e8S5h/OSUd18tX2MoFTiLBGQJEzmdCTo0bMPP0qvDJXXK4XW ikH5fluWyAkAtxbeNt5INEFIeJSRCs37l8URi0nXkSDM/fD8hJgK3hyKdNDswIjfxr +gmMbW+u+2SlR5EGnYVwgC0+mUqG0k69lUO1XaMhlsn9OHc6hxv15ZX4aGfs/0e1AQ 0ly/2dgoBAxGjuPUGqT3PeyD2c9pdmQe/7w2Pxkrx1HI3KOkn3zqfh/+ez+YOirJ1m sCEUUqXhttcu2kA/LEMuDJVJYCW6rhQ/xTqsXvfOguTsY51kY8K25ExXItqTWRes7h VZFcb5/hEa2NQ== Mime-Version: 1.0 Content-Type: multipart/signed; boundary=435a6584ef4073aabfcab6581759a06710d32f98fed9f451cfc176f00a13; micalg=pgp-sha384; protocol="application/pgp-signature" Date: Thu, 12 Mar 2026 09:46:44 +0100 Message-Id: Subject: Re: [PATCH 2/2] ili9806e: Add Densitron DMT050WVNMCMI-1A to ILI9806E DSI driver From: "Michael Walle" To: =?utf-8?q?Bartholom=C3=A4us_Steinmayr?= , "dri-devel@lists.freedesktop.org" Content-Transfer-Encoding: quoted-printable X-Mailer: aerc 0.20.0 References: In-Reply-To: X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" --435a6584ef4073aabfcab6581759a06710d32f98fed9f451cfc176f00a13 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Hi, just some random remarks, not a complete review. On Wed Mar 11, 2026 at 4:55 PM CET, Bartholom=C3=A4us Steinmayr wrote: > Add Densitron DMT050WVNMCMI-1A to ILI9806E DSI=20 > Add i2c-frag to allow probe deferral until Goodix touchpanel chip in the= =20 > display is initialized. Make reset-gpios optional to allow delegation of= =20 > reset to Goodix driver.=20 > > Signed-off-by: Bart Steinmayr > --- > drivers/gpu/drm/panel/panel-ilitek-ili9806e.c | 202 +++++++++++++++++- > 1 file changed, 201 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/panel/panel-ilitek-ili9806e.c b/drivers/gpu/= drm/panel/panel-ilitek-ili9806e.c > index 18aa6222b0c5..ce77ee7cbc10 100644 > --- a/drivers/gpu/drm/panel/panel-ilitek-ili9806e.c > +++ b/drivers/gpu/drm/panel/panel-ilitek-ili9806e.c > @@ -10,6 +10,9 @@ > #include > #include > #include > +#include > + > +#include > =20 > #include > #include > @@ -166,6 +169,22 @@ static int ili9806e_dsi_probe(struct mipi_dsi_device= *dsi) > struct ili9806e_panel *ctx; > int i, ret; > =20 > + struct device_node *i2c_frag =3D of_parse_phandle(dev->of_node, "i2c-fr= ag", 0); > + > + if (i2c_frag) { > + void *i2c_driver_data =3D NULL; > + > + struct i2c_client *i2c_frag_client =3D of_find_i2c_device_by_node(i2c_= frag); > + > + of_node_put(i2c_frag); > + if (i2c_frag_client) { > + i2c_driver_data =3D dev_get_drvdata(&i2c_frag_client->dev); > + put_device(&i2c_frag_client->dev); > + } > + if (!i2c_driver_data) > + return dev_err_probe(dev, -EPROBE_DEFER, "failed to get i2c-frag\n"); > + } > + > ctx =3D devm_drm_panel_alloc(dev, struct ili9806e_panel, panel, &ili980= 6e_funcs, > DRM_MODE_CONNECTOR_DSI); > if (IS_ERR(ctx)) > @@ -181,7 +200,7 @@ static int ili9806e_dsi_probe(struct mipi_dsi_device = *dsi) > if (ret < 0) > return ret; > =20 > - ctx->reset_gpio =3D devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); > + ctx->reset_gpio =3D devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW= ); As mentioned in my previous reply. I'm not really sure this will work. Do you have a regulator attached and described in the device tree? First, that will still be disabled and not having a reset then is bad. Also I guess the init sequeuce will still be run if the panel is turned off and on again. And then there will be no reset to defaults. > if (IS_ERR(ctx->reset_gpio)) > return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio), > "Failed to get reset-gpios\n"); > @@ -542,8 +561,188 @@ static const struct panel_desc dmt028vghmcmi_1d_des= c =3D { > .lanes =3D 2, > }; > =20 > +static u8 dsi_read(struct mipi_dsi_multi_context *ctx, u8 command) > +{ > + struct mipi_dsi_device *dsi =3D ctx->dsi; > + > + u8 len =3D 1; > + u8 result_data =3D 0xFF; Use lower case, as you've already did below. > + > + mipi_dsi_set_maximum_return_packet_size(dsi, 1); > + mipi_dsi_dcs_read(dsi, command, &result_data, len); > + > + return result_data; > +} > + > +static void dmt050wvnmcmi_1a_init(struct mipi_dsi_multi_context *ctx) > +{ > + // Try to read pixel format to check display connection Use C comments /* */ > + u8 pixel_format =3D dsi_read(ctx, 0x0c); Also this is just used once. You could just use the two commands here. "dsi_read" is a pretty common name which might cause aliasing issues in the future. > + > + if (pixel_format !=3D 0x70) > + dev_err(&ctx->dsi->dev, "Read pixel format failed: %d\n", pixel_format= ); So? No return? Just an error message? Also if you happen to know what 0x70 is, please either add a define or a comment. > + > + mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x01); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x08, 0x10); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x20, 0x00); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x01); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x30, 0x01); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x31, 0x00); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x40, 0x16); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x41, 0x33); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x42, 0x03); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x43, 0x09); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x44, 0x06); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x50, 0x88); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x51, 0x88); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x52, 0x00); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x53, 0x49); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x55, 0x49); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x60, 0x07); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x61, 0x00); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x62, 0x07); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x63, 0x00); > + > + //Positive Gamma > + mipi_dsi_dcs_write_seq_multi(ctx, 0xA0, 0x00); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xA1, 0x09); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xA2, 0x11); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xA3, 0x0B); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xA4, 0x05); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xA5, 0x08); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xA6, 0x06); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xA7, 0x04); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xA8, 0x09); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xA9, 0x0C); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xAA, 0x15); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xAB, 0x08); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xAC, 0x0F); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xAD, 0x12); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xAE, 0x09); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xAF, 0x00); > + > + //Negative Gamma > + mipi_dsi_dcs_write_seq_multi(ctx, 0xC0, 0x00); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xC1, 0x09); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xC2, 0x10); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xC3, 0x0C); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xC4, 0x05); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xC5, 0x08); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xC6, 0x06); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xC7, 0x04); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xC8, 0x08); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xC9, 0x0C); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xCA, 0x14); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xCB, 0x08); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xCC, 0x0F); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xCD, 0x11); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xCE, 0x09); > + mipi_dsi_dcs_write_seq_multi(ctx, 0xCF, 0x00); > + > + mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x6); > + > + mipi_dsi_dcs_write_seq_multi(ctx, 0x00, 0x20); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x01, 0x0A); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x02, 0x00); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x03, 0x00); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x04, 0x01); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x05, 0x01); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x06, 0x98); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x07, 0x06); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x08, 0x01); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x09, 0x80); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x0A, 0x00); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x0B, 0x00); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x0C, 0x01); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x0D, 0x01); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x0E, 0x05); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x0F, 0x00); > + > + mipi_dsi_dcs_write_seq_multi(ctx, 0x10, 0xF0); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x11, 0xF4); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x12, 0x01); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x13, 0x00); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x14, 0x00); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x15, 0xC0); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x16, 0x08); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x17, 0x00); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x18, 0x00); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x19, 0x00); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x1A, 0x00); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x1B, 0x00); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x1C, 0x00); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x1D, 0x00); > + > + mipi_dsi_dcs_write_seq_multi(ctx, 0x20, 0x01); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x21, 0x23); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x22, 0x45); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x23, 0x67); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x24, 0x01); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x25, 0x23); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x26, 0x45); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x27, 0x67); > + > + mipi_dsi_dcs_write_seq_multi(ctx, 0x30, 0x11); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x31, 0x11); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x32, 0x00); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x33, 0xEE); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x34, 0xFF); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x35, 0xBB); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x36, 0xAA); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x37, 0xDD); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x38, 0xCC); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x39, 0x66); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x3A, 0x77); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x3B, 0x22); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x3C, 0x22); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x3D, 0x22); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x3E, 0x22); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x3F, 0x22); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x40, 0x22); > + > + mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x07); > + > + mipi_dsi_dcs_write_seq_multi(ctx, 0x17, 0x22); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x02, 0x77); > + mipi_dsi_dcs_write_seq_multi(ctx, 0x26, 0xB2); > + > + mipi_dsi_dcs_write_seq_multi(ctx, 0xff, 0xff, 0x98, 0x06, 0x04, 0x00); > + > + mipi_dsi_dcs_write_seq_multi(ctx, 0x3A, 0x70); //Data format RGB24 For all the numbers above, please use lower case to match the style of this file. -michael > +}; > + > +static const struct drm_display_mode dmt050wvnmcmi_1a_default_mode =3D { > + .clock =3D 41666, > + > + .hdisplay =3D 480, > + .hsync_start =3D 480 + 100, > + .hsync_end =3D 480 + 100 + 10, > + .htotal =3D 480 + 100 + 10 + 50, > + > + .vdisplay =3D 854, > + .vsync_start =3D 854 + 20, > + .vsync_end =3D 854 + 20 + 4, > + .vtotal =3D 854 + 20 + 4 + 20, > + > + .width_mm =3D 61, > + .height_mm =3D 109, > + > + .flags =3D DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC, > + .type =3D DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, > +}; > + > +static const struct panel_desc dmt050wvnmcmi_1a_desc =3D { > + .init_sequence =3D dmt050wvnmcmi_1a_init, > + .display_mode =3D &dmt050wvnmcmi_1a_default_mode, > + .mode_flags =3D MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | > + MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS, > + .format =3D MIPI_DSI_FMT_RGB888, > + .lanes =3D 2, > +}; > + > static const struct of_device_id ili9806e_of_match[] =3D { > { .compatible =3D "densitron,dmt028vghmcmi-1d", .data =3D &dmt028vghmcm= i_1d_desc }, > + { .compatible =3D "densitron,dmt050wvnmcmi-1a", .data =3D &dmt050wvnmcm= i_1a_desc }, > { .compatible =3D "ortustech,com35h3p70ulc", .data =3D &com35h3p70ulc_d= esc }, > { } > }; > @@ -561,5 +760,6 @@ module_mipi_dsi_driver(ili9806e_dsi_driver); > =20 > MODULE_AUTHOR("Gunnar Dibbern "); > MODULE_AUTHOR("Michael Walle "); > +MODULE_AUTHOR("Bart Steinmayr "); > MODULE_DESCRIPTION("Ilitek ILI9806E Controller Driver"); > MODULE_LICENSE("GPL"); --435a6584ef4073aabfcab6581759a06710d32f98fed9f451cfc176f00a13 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iKgEABMJADAWIQTIVZIcOo5wfU/AngkSJzzuPgIf+AUCabJ9iBIcbXdhbGxlQGtl cm5lbC5vcmcACgkQEic87j4CH/iIMgF/d1Vqd6hsl/JZbQ7EIqWJGR/yP8kfFmL9 7XDyr9019AQJKotRLkVia32wU7bxoxh9AYCASF77c+YAfDCoLAjoyMew9rNeMK9A LT2R01SUWZschKgQm+77VYte2srT9po/xV0= =ssCY -----END PGP SIGNATURE----- --435a6584ef4073aabfcab6581759a06710d32f98fed9f451cfc176f00a13--