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Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Wed, 11 Nov 2026 23:49:57 +0900 Message-Id: Cc: "Danilo Krummrich" , "Alice Ryhl" , "David Airlie" , "Simona Vetter" , "John Hubbard" , "Alistair Popple" , "Timur Tabi" , , , Subject: Re: [PATCH 2/2] gpu: nova-core: gsp: cmdq: increase MSGQ_NUM_PAGES to 64 From: "Alexandre Courbot" To: "Eliot Courtney" References: <20261111-msgq-64-pages-v1-0-d8c56b6fdd6c@nvidia.com> <20261111-msgq-64-pages-v1-2-d8c56b6fdd6c@nvidia.com> In-Reply-To: <20261111-msgq-64-pages-v1-2-d8c56b6fdd6c@nvidia.com> X-ClientProxiedBy: TYCP286CA0317.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:3b7::7) To MW4PR12MB6873.namprd12.prod.outlook.com (2603:10b6:303:20c::17) X-Archived-By: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MW4PR12MB6873:EE_|IA6PR12MB765073:EE_ X-MS-Office365-Filtering-Correlation-Id: 50a71177-f918-4be1-4e91-08df40030fe3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 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X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ZKsG8i1wWlpZfO+N3YKErhLgptPNUE8Wbud0KxCFmfFF9q8lSDwJ0jtwaTdgLtEpD85ykngmmrhLvXW/JNEBTA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA6PR12MB765073 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "dri-devel" X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=unavailable autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Wed Nov 11, 2026 at 10:37 AM JST, Eliot Courtney wrote: > In the msgq v2 protocol, which the r000 firmware uses, the queue > pointers are kept in u32 registers and increase monotonically until they > wrap at 2^32. > > `MSGQ_NUM_PAGES` is currently 63 and does not divide 2^32. This means > that on msgq v2, the slot can jump backwards when the counters wrap. > For example: > > (2^32 - 2) % 63 =3D=3D 2 > (2^32 - 1) % 63 =3D=3D 3 > 0 % 63 =3D=3D 0 (slot 0 instead of slot 4) > > The writer can then overwrite slots before the reader has read them. > > Increase `MSGQ_NUM_PAGES` to 64 and check at compile time that > `MSGQ_NUM_PAGES` divides 2^32. Have we tested that this was also working on msgq v0? > > Signed-off-by: Eliot Courtney > --- > drivers/gpu/nova-core/gsp/cmdq.rs | 10 +++++++++- > 1 file changed, 9 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/nova-core/gsp/cmdq.rs b/drivers/gpu/nova-core/gs= p/cmdq.rs > index 33074bb53e8c..240ab42db557 100644 > --- a/drivers/gpu/nova-core/gsp/cmdq.rs > +++ b/drivers/gpu/nova-core/gsp/cmdq.rs > @@ -84,7 +84,15 @@ trait CommandElement { > } > =20 > /// Number of GSP pages making the [`Msgq`]. > -pub(crate) const MSGQ_NUM_PAGES: u32 =3D 0x3f; > +pub(crate) const MSGQ_NUM_PAGES: u32 =3D 64; > + > +// From version 2 of the msgq protocol, the queue pointers increase > +// monotonically in `u32` counters until they wrap. If `MSGQ_NUM_PAGES` = does not > +// divide `1 << 32`, then the slot, `counter % MSGQ_NUM_PAGES`, can jump > +// backwards when wrapping, which could overwrite slots that still need = to be > +// read. So, require that the last counter value, `u32::MAX`, maps to th= e last > +// slot. That's a pretty convoluted way to say the number of slots must be a power of 2 representable as a u32. :) > +static_assert!(u32::MAX % MSGQ_NUM_PAGES =3D=3D MSGQ_NUM_PAGES - 1); Same here, can't we use `MSGQ_NUM_PAGES.is_power_of_two()`?