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[31.178.127.80]) by smtp.gmail.com with ESMTPSA id q12-20020a056512210c00b00489daae997fsm355423lfr.10.2022.07.10.10.01.20 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 10 Jul 2022 10:01:21 -0700 (PDT) Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (Mac OS X Mail 14.0 \(3654.120.0.1.13\)) Subject: Re: [PATCH v11 20/24] arm64: dts: rockchip: enable vop2 and hdmi tx on rock-3a From: Piotr Oniszczuk In-Reply-To: Date: Sun, 10 Jul 2022 19:01:17 +0200 Content-Transfer-Encoding: quoted-printable Message-Id: References: <20220422072841.2206452-1-s.hauer@pengutronix.de> <20220422072841.2206452-21-s.hauer@pengutronix.de> <0E6FE020-C95E-47CF-A9D6-AC3F2B2D334F@gmail.com> <9F2D8CFF-1EAE-4586-9EE9-82A9D67840BB@gmail.com> <9567EECF-A154-4FE1-A03C-5ED080409030@gmail.com> <190C3FD3-0185-4A99-B10E-A5790047D993@gmail.com> <0D8B18A1-82FD-4902-A443-AD774DE43DAD@gmail.com> To: Peter Geis X-Mailer: Apple Mail (2.3654.120.0.1.13) X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "devicetree@vger.kernel.org" , Benjamin Gaignard , Sascha Hauer , Sandy Huang , dri-devel@lists.freedesktop.org, "open list:ARM/Rockchip SoC..." , Michael Riesch , kernel@pengutronix.de, Andy Yan , "linux-arm-kernel@lists.infradead.org" , kernel test robot Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" > Wiadomo=C5=9B=C4=87 napisana przez Piotr Oniszczuk = w dniu 25.06.2022, o godz. 17:31: >=20 >=20 >=20 >> Wiadomo=C5=9B=C4=87 napisana przez Peter Geis w = dniu 25.06.2022, o godz. 16:00: >>=20 >>=20 >> The first issue you have is the TV isn't responding until the = absolute >> end. >=20 > I suspect this is because lack on idle gaps between cec commands sent = from board to tv. > Maybe TV sw. can't deal with consecutive commands without any idle = between them?=20 >=20 > It is interesting that disconnecting TV - so CEC line is driven only = by board - rock3a still don't have any idle gaps while rock3b (and radxa = 4.19 bsp) has them (very similar between 5.18mailine and 4.19 bsp). >=20 > How this is possible that change I/O from m0->m1 impacts _timings_ on = free hanging CEC line?=20 >=20 >> This strikes me as a signal integrity issue. Do you have an >> oscilloscope (not a logic analyzer, you need voltages and ramp times) >> to compare the working vs non-working signals? Check both sides of = the >> level shifter. >=20 > Indeed - i will verify this with digital oscilloscope.=20 Peter, fyi I got my oscilloscope and do measurements on hdmi cable cec line on: = working rock3b and non-working rock3a. sw was exactly the same (same sd card; only dtb changed) Pls see measurements for: start pulse "0" pulse "1" pulse non-working rock3-a: http://warped.inet2.org/rock3a-one.png http://warped.inet2.org/rock3a-start.png http://warped.inet2.org/rock3a-zero.png working rock3-b http://warped.inet2.org/rock3b-one.png http://warped.inet2.org/rock3b-start.png http://warped.inet2.org/rock3b-zero.png Now i'm 99% sure issue is not hw related but sw (kernel)... br=