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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id z6sm391592oiz.39.2021.07.26.21.23.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Jul 2021 21:23:24 -0700 (PDT) Date: Mon, 26 Jul 2021 21:21:35 -0700 From: Bjorn Andersson To: Rob Clark Subject: Re: [PATCH] drm/msm: Fix display fault handling Message-ID: References: <20210707180113.840741-1-robdclark@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210707180113.840741-1-robdclark@gmail.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , "open list:DRM DRIVER FOR MSM ADRENO GPU" , Yassine Oudjana , David Airlie , "open list:DRM DRIVER FOR MSM ADRENO GPU" , open list , dri-devel@lists.freedesktop.org, Jordan Crouse , Dmitry Baryshkov , Sean Paul Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Wed 07 Jul 11:01 PDT 2021, Rob Clark wrote: > From: Rob Clark > > It turns out that when the display is enabled by the bootloader, we can > get some transient iommu faults from the display. Which doesn't go over > too well when we install a fault handler that is gpu specific. To avoid > this, defer installing the fault handler until we get around to setting > up per-process pgtables (which is adreno_smmu specific). The arm-smmu > fallback error reporting is sufficient for reporting display related > faults (and in fact was all we had prior to f8f934c180f629bb927a04fd90d) > > Reported-by: Dmitry Baryshkov > Reported-by: Yassine Oudjana > Fixes: 2a574cc05d38 ("drm/msm: Improve the a6xx page fault handler") > Signed-off-by: Rob Clark > Tested-by: John Stultz Reviewed-by: Bjorn Andersson Regards, Bjorn > --- > drivers/gpu/drm/msm/msm_iommu.c | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c > index eed2a762e9dd..bcaddbba564d 100644 > --- a/drivers/gpu/drm/msm/msm_iommu.c > +++ b/drivers/gpu/drm/msm/msm_iommu.c > @@ -142,6 +142,9 @@ static const struct iommu_flush_ops null_tlb_ops = { > .tlb_add_page = msm_iommu_tlb_add_page, > }; > > +static int msm_fault_handler(struct iommu_domain *domain, struct device *dev, > + unsigned long iova, int flags, void *arg); > + > struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent) > { > struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(parent->dev); > @@ -157,6 +160,13 @@ struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent) > if (!ttbr1_cfg) > return ERR_PTR(-ENODEV); > > + /* > + * Defer setting the fault handler until we have a valid adreno_smmu > + * to avoid accidentially installing a GPU specific fault handler for > + * the display's iommu > + */ > + iommu_set_fault_handler(iommu->domain, msm_fault_handler, iommu); > + > pagetable = kzalloc(sizeof(*pagetable), GFP_KERNEL); > if (!pagetable) > return ERR_PTR(-ENOMEM); > @@ -300,7 +310,6 @@ struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain) > > iommu->domain = domain; > msm_mmu_init(&iommu->base, dev, &funcs, MSM_MMU_IOMMU); > - iommu_set_fault_handler(domain, msm_fault_handler, iommu); > > atomic_set(&iommu->pagetables, 0); > > -- > 2.31.1 >