From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 94471C433FE for ; Wed, 6 Oct 2021 12:22:05 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 63FD7610A2 for ; Wed, 6 Oct 2021 12:22:05 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 63FD7610A2 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 65A616ECD4; Wed, 6 Oct 2021 12:22:04 +0000 (UTC) Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by gabe.freedesktop.org (Postfix) with ESMTPS id 285FB6E4B7; Wed, 6 Oct 2021 12:22:03 +0000 (UTC) Received: by mail.kernel.org (Postfix) with ESMTPSA id 0F2F861076; Wed, 6 Oct 2021 12:22:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1633522923; bh=GjdXB4CBUTuCHgg5ae5o/noPoLm1nYBZkINiNMaM/Lw=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=oe3odlBcQJ0FczNrgKkyoY6iP7j0ia588/hsTfirbe2FPWn7EcLFZjrt7emFkzQAS OOs1CPIrO1W+HiEyhDihKT1fxEbzrC2L7fiDEgUOEnXAcA0UL7bWhVzRA0AAWd1Ltn NYXRVKSnqwhc+ieE2kvbMs61jDc3Q4Cmyl7btdKDDX4Ks/o3VxHAbR4PrOG/VXEXU+ wjyEHPOO4xbuQ0TgwLf/WA6KgEZJ9StY6PlZSj0A/C0CPVaCMQCwvtEKhoKUC2pnUA e7WZ0AJpbBa0yymINx64YOt18RitlcoTgGO7t7PRxyx4fcZApccMc/qTIxmdhS6ngQ XIlZf6h8k18xw== Date: Wed, 6 Oct 2021 17:51:59 +0530 From: Vinod Koul To: abhinavk@codeaurora.org Cc: Rob Clark , Jonathan Marek , Jeffrey Hugo , David Airlie , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Bjorn Andersson , dri-devel@lists.freedesktop.org, Daniel Vetter , Dmitry Baryshkov , freedreno@lists.freedesktop.org, Sumit Semwal Subject: Re: [Freedreno] [PATCH 06/11] drm/msm/disp/dpu1: Add DSC support in hw_ctl Message-ID: References: <20210715065203.709914-1-vkoul@kernel.org> <20210715065203.709914-7-vkoul@kernel.org> <7317c6b71043267ce19b7826502c9735@codeaurora.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <7317c6b71043267ce19b7826502c9735@codeaurora.org> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On 02-08-21, 17:00, abhinavk@codeaurora.org wrote: > On 2021-07-14 23:51, Vinod Koul wrote: > > Later gens of hardware have DSC bits moved to hw_ctl, so configure these > > bits so that DSC would work there as well > > > > Signed-off-by: Vinod Koul > Please correct me if wrong but here you seem to be flushing all the DSC bits > even the unused ones. This will end-up enabling DSC even when DSC is unused > on > the newer targets. > If so, thats wrong. > We need to implement bit-mask based approach to avoid this change and only > enable > those DSCs which are used. Yes as Dimitry suggested I have done that by passing indices -- ~Vinod