From: Thierry Reding <thierry.reding@gmail.com>
To: Dmitry Osipenko <digetx@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>,
Maxim Schwalm <maxim.schwalm@gmail.com>,
dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org
Subject: Re: [PATCH v1 1/2] drm/tegra: dc: rgb: Move PCLK shifter programming to CRTC
Date: Wed, 6 Oct 2021 20:10:45 +0200 [thread overview]
Message-ID: <YV3mpcyZH3gox1Sl@orome.fritz.box> (raw)
In-Reply-To: <20210929222805.16511-2-digetx@gmail.com>
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On Thu, Sep 30, 2021 at 01:28:04AM +0300, Dmitry Osipenko wrote:
> Asus TF700T tablet uses TC358768 DPI->DSI bridge that sits between Tegra's
> DPI output and display panel input. Bridge requires to have stable PCLK
> output before RGB encoder is enabled because it uses PCLK by itself to
> clock internal logic and bridge is programmed before Tegra's encoder is
> enabled. Hence the PCLK clock shifter must be programmed when CRTC is
> enabled, otherwise clock is unstable and bridge hangs because of it.
> Move the shifter programming from RGB encoder into CRTC.
>
> Tested-by: Maxim Schwalm <maxim.schwalm@gmail.com> #TF700T
> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> ---
> drivers/gpu/drm/tegra/dc.c | 6 ++++++
> drivers/gpu/drm/tegra/rgb.c | 4 ----
> 2 files changed, 6 insertions(+), 4 deletions(-)
Applied, thanks.
Thierry
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next prev parent reply other threads:[~2021-10-06 18:10 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-29 22:28 [PATCH v1 0/2] NVIDIA Tegra display driver improvements Dmitry Osipenko
2021-09-29 22:28 ` [PATCH v1 1/2] drm/tegra: dc: rgb: Move PCLK shifter programming to CRTC Dmitry Osipenko
2021-10-06 18:10 ` Thierry Reding [this message]
2021-09-29 22:28 ` [PATCH v1 2/2] drm/tegra: dc: rgb: Allow changing PLLD rate on Tegra30+ Dmitry Osipenko
2021-10-06 18:13 ` Thierry Reding
2021-10-06 18:27 ` Dmitry Osipenko
2021-10-06 21:07 ` Dmitry Osipenko
2021-10-08 19:35 ` Thierry Reding
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