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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id a6sm4198301oil.6.2021.12.28.15.11.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Dec 2021 15:11:26 -0800 (PST) Date: Tue, 28 Dec 2021 15:12:27 -0800 From: Bjorn Andersson To: Kuogee Hsieh Subject: Re: [PATCH] drm/msm/dp: add support of tps4 (training pattern 4) for HBR3 Message-ID: References: <1640717489-7366-1-git-send-email-quic_khsieh@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1640717489-7366-1-git-send-email-quic_khsieh@quicinc.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: quic_sbillaka@quicinc.com, quic_abhinavk@quicinc.com, airlied@linux.ie, freedreno@lists.freedesktop.org, vkoul@kernel.org, dri-devel@lists.freedesktop.org, swboyd@chromium.org, Kuogee Hsieh , agross@kernel.org, linux-arm-msm@vger.kernel.org, dmitry.baryshkov@linaro.org, aravindh@codeaurora.org, sean@poorly.run, linux-kernel@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Tue 28 Dec 10:51 PST 2021, Kuogee Hsieh wrote: > From: Kuogee Hsieh > > Some DP sinkers prefer to use tps4 instead of tps3 during training #2. > This patch will use tps4 to perform link training #2 if sinker's DPCD > supports it. > > Signed-off-by: Kuogee Hsieh > --- > drivers/gpu/drm/msm/dp/dp_ctrl.c | 16 ++++++++++++---- > 1 file changed, 12 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c > index 39558a2..c7b0657 100644 > --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c > +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c > @@ -1181,7 +1181,7 @@ static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, > int *training_step) > { > int tries = 0, ret = 0; > - char pattern; > + char pattern, state_ctrl_bit; > int const maximum_retries = 5; > u8 link_status[DP_LINK_STATUS_SIZE]; > > @@ -1189,12 +1189,20 @@ static int dp_ctrl_link_train_2(struct dp_ctrl_private *ctrl, > > *training_step = DP_TRAINING_2; > > - if (drm_dp_tps3_supported(ctrl->panel->dpcd)) > + if (drm_dp_tps4_supported(ctrl->panel->dpcd)) { > + pattern = DP_TRAINING_PATTERN_4; > + state_ctrl_bit = 4; > + } > + else if (drm_dp_tps3_supported(ctrl->panel->dpcd)) { > pattern = DP_TRAINING_PATTERN_3; > - else > + state_ctrl_bit = 3; > + } > + else { > pattern = DP_TRAINING_PATTERN_2; > + state_ctrl_bit = 2; > + } > > - ret = dp_catalog_ctrl_set_pattern(ctrl->catalog, pattern); > + ret = dp_catalog_ctrl_set_pattern(ctrl->catalog, state_ctrl_bit); The patch looks good, but as the state_ctrl_bit is no longer equal to DP_PATTERN_n the function and argument names are misleading. Please rename it to something like "dp_catalog_ctrl_set_pattern_state_bit()" and the "pattern" argument within that function to "state_bit". Thanks, Bjorn > if (ret) > return ret; > > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project >