Re: [PATCH 09/27] drm/rockchip: dw_hdmi: Set cur_ctr to 0 always

Doug Anderson
2022-01-26T15:43:05Z

Hi,

On Wed, Jan 26, 2022 at 6:58 AM Sascha Hauer <s.hauer@pengutronix.de> wrote:
>
> From: Douglas Anderson <dianders@chromium.org>
>
> Jitter was improved by lowering the MPLL bandwidth to account for high
> frequency noise in the rk3288 PLL. In each case MPLL bandwidth was
> lowered only enough to get us a comfortable margin. We believe that
> lowering the bandwidth like this is safe given sufficient testing.
>
> Changes since v3:
> - new patch
>
> Signed-off-by: Douglas Anderson <dianders@chromium.org>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> (am from https://patchwork.kernel.org/patch/9223301/)

Probably remove the "am from" line? It's not standard in upstream and
that link doesn't seem to go anywhere anymore...

> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 16 ++--------------
> 1 file changed, 2 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> index c44eb4d2e2d5..77f82a4fd027 100644
> --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
> @@ -176,20 +176,8 @@ static const struct dw_hdmi_mpll_config rockchip_mpll_cfg[] = {
> static const struct dw_hdmi_curr_ctrl rockchip_cur_ctr[] = {
> /* pixelclk bpp8 bpp10 bpp12 */
> {
> - 40000000, { 0x0018, 0x0018, 0x0018 },
> - }, {
> - 65000000, { 0x0028, 0x0028, 0x0028 },
> - }, {
> - 66000000, { 0x0038, 0x0038, 0x0038 },
> - }, {
> - 74250000, { 0x0028, 0x0038, 0x0038 },
> - }, {
> - 83500000, { 0x0028, 0x0038, 0x0038 },
> - }, {
> - 146250000, { 0x0038, 0x0038, 0x0038 },
> - }, {
> - 148500000, { 0x0000, 0x0038, 0x0038 },
> - }, {
> + 600000000, { 0x0000, 0x0000, 0x0000 },
> + }, {

This is what we did for rk3288. I can't personally vouch for the
effects on other SoCs.

-Doug