From: Alyssa Rosenzweig <alyssa@collabora.com>
To: Adri??n Larumbe <adrian.larumbe@collabora.com>
Cc: dri-devel@lists.freedesktop.org, alyssa.rosenzweig@collabora.com,
tomeu.vizoso@collabora.com, steven.price@arm.com
Subject: Re: [PATCH v4 1/2] drm/panfrost: Add specific register offset macros for JS and MMU AS
Date: Wed, 22 Jun 2022 11:09:36 -0400 [thread overview]
Message-ID: <YrMwsFCWOXeLUM7w@maud> (raw)
In-Reply-To: <20220622143616.1265405-2-adrian.larumbe@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
On Wed, Jun 22, 2022 at 03:36:15PM +0100, Adri??n Larumbe wrote:
> Each Panfrost job has its own job slot and MMU address space set of
> registers, which are selected with a job-specific index.
>
> Turn the shift and stride used for selection of the right register set base
> into a define rather than using magic numbers.
>
> Signed-off-by: Adri??n Larumbe <adrian.larumbe@collabora.com>
> ---
> drivers/gpu/drm/panfrost/panfrost_regs.h | 39 +++++++++++++-----------
> 1 file changed, 21 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/panfrost/panfrost_regs.h b/drivers/gpu/drm/panfrost/panfrost_regs.h
> index accb4fa3adb8..1ddc6c4c5e1c 100644
> --- a/drivers/gpu/drm/panfrost/panfrost_regs.h
> +++ b/drivers/gpu/drm/panfrost/panfrost_regs.h
> @@ -225,24 +225,26 @@
> #define JOB_INT_MASK_ERR(j) BIT((j) + 16)
> #define JOB_INT_MASK_DONE(j) BIT(j)
>
> +#define JS_SLOT_STRIDE 0x80
> +
> #define JS_BASE 0x1800
> -#define JS_HEAD_LO(n) (JS_BASE + ((n) * 0x80) + 0x00)
> -#define JS_HEAD_HI(n) (JS_BASE + ((n) * 0x80) + 0x04)
> -#define JS_TAIL_LO(n) (JS_BASE + ((n) * 0x80) + 0x08)
> -#define JS_TAIL_HI(n) (JS_BASE + ((n) * 0x80) + 0x0c)
> -#define JS_AFFINITY_LO(n) (JS_BASE + ((n) * 0x80) + 0x10)
> -#define JS_AFFINITY_HI(n) (JS_BASE + ((n) * 0x80) + 0x14)
> -#define JS_CONFIG(n) (JS_BASE + ((n) * 0x80) + 0x18)
> -#define JS_XAFFINITY(n) (JS_BASE + ((n) * 0x80) + 0x1c)
> -#define JS_COMMAND(n) (JS_BASE + ((n) * 0x80) + 0x20)
> -#define JS_STATUS(n) (JS_BASE + ((n) * 0x80) + 0x24)
> -#define JS_HEAD_NEXT_LO(n) (JS_BASE + ((n) * 0x80) + 0x40)
> -#define JS_HEAD_NEXT_HI(n) (JS_BASE + ((n) * 0x80) + 0x44)
> -#define JS_AFFINITY_NEXT_LO(n) (JS_BASE + ((n) * 0x80) + 0x50)
> -#define JS_AFFINITY_NEXT_HI(n) (JS_BASE + ((n) * 0x80) + 0x54)
> -#define JS_CONFIG_NEXT(n) (JS_BASE + ((n) * 0x80) + 0x58)
> -#define JS_COMMAND_NEXT(n) (JS_BASE + ((n) * 0x80) + 0x60)
> -#define JS_FLUSH_ID_NEXT(n) (JS_BASE + ((n) * 0x80) + 0x70)
> +#define JS_HEAD_LO(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x00)
> +#define JS_HEAD_HI(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x04)
> +#define JS_TAIL_LO(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x08)
> +#define JS_TAIL_HI(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x0c)
> +#define JS_AFFINITY_LO(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x10)
> +#define JS_AFFINITY_HI(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x14)
> +#define JS_CONFIG(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x18)
> +#define JS_XAFFINITY(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x1c)
> +#define JS_COMMAND(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x20)
> +#define JS_STATUS(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x24)
> +#define JS_HEAD_NEXT_LO(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x40)
> +#define JS_HEAD_NEXT_HI(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x44)
> +#define JS_AFFINITY_NEXT_LO(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x50)
> +#define JS_AFFINITY_NEXT_HI(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x54)
> +#define JS_CONFIG_NEXT(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x58)
> +#define JS_COMMAND_NEXT(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x60)
> +#define JS_FLUSH_ID_NEXT(n) (JS_BASE + ((n) * JS_SLOT_STRIDE) + 0x70)
>
> /* Possible values of JS_CONFIG and JS_CONFIG_NEXT registers */
> #define JS_CONFIG_START_FLUSH_CLEAN BIT(8)
> @@ -281,7 +283,8 @@
> #define AS_COMMAND_FLUSH_MEM 0x05 /* Wait for memory accesses to complete, flush all the L1s cache then
> flush all L2 caches then issue a flush region command to all MMUs */
>
> -#define MMU_AS(as) (0x2400 + ((as) << 6))
> +#define MMU_AS_SHIFT 0x06
> +#define MMU_AS(as) (0x2400 + ((as) << MMU_AS_SHIFT))
>
> #define AS_TRANSTAB_LO(as) (MMU_AS(as) + 0x00) /* (RW) Translation Table Base Address for address space n, low word */
> #define AS_TRANSTAB_HI(as) (MMU_AS(as) + 0x04) /* (RW) Translation Table Base Address for address space n, high word */
> --
> 2.36.1
>
next prev parent reply other threads:[~2022-06-22 15:09 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-22 14:36 [PATCH v4 0/2] devcoredump support for Panfrost GPU driver Adrián Larumbe
2022-06-22 14:36 ` [PATCH v4 1/2] drm/panfrost: Add specific register offset macros for JS and MMU AS Adrián Larumbe
2022-06-22 15:09 ` Alyssa Rosenzweig [this message]
2022-06-23 12:23 ` Steven Price
2022-06-22 14:36 ` [PATCH v4 2/2] drm/panfrost: Add support for devcoredump Adrián Larumbe
2022-06-23 12:23 ` Steven Price
2022-07-18 16:30 ` Adrián Larumbe
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