From: Sam Ravnborg <sam@ravnborg.org>
To: Dave Stevenson <dave.stevenson@raspberrypi.com>
Cc: Marek Vasut <marex@denx.de>,
Jagan Teki <jagan@amarulasolutions.com>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Thomas Zimmermann <tzimmermann@suse.de>,
Jonas Karlman <jonas@kwiboo.se>, David Airlie <airlied@linux.ie>,
Robert Foss <robert.foss@linaro.org>,
Neil Armstrong <narmstrong@baylibre.com>,
Douglas Anderson <dianders@chromium.org>,
dri-devel@lists.freedesktop.org,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Andrzej Hajda <andrzej.hajda@intel.com>,
andrzej.hajda@gmail.com,
Laurent Pinchart <Laurent.pinchart@ideasonboard.com>
Subject: Re: [PATCH V2 0/3] DSI host and peripheral initialisation ordering
Date: Mon, 18 Jul 2022 22:52:34 +0200 [thread overview]
Message-ID: <YtXIEg0rRZLLYS75@ravnborg.org> (raw)
In-Reply-To: <cover.1646406653.git.dave.stevenson@raspberrypi.com>
Hi Dave,
a long overdue reply on this series.
On Fri, Mar 04, 2022 at 03:17:55PM +0000, Dave Stevenson wrote:
> Hi All
>
> Changes from v1:
> - New patch to refactor drm_bridge_chain_post_disable and drm_bridge_chain_pre_enable
> to reuse drm_atomic_bridge_chain_post_disable / drm_atomic_bridge_chain_pre_enable
> but with a NULL state.
> - New patch that adds a pre_enable_upstream_first to drm_panel.
> - changed from an OPS flag to a bool "pre_enable_upstream_first" in drm_bridge.
> - Followed Andrzej's suggestion of using continue in the main loop to avoid
> needing 2 additional loops (one forward to find the last bridge wanting
> upstream first, and the second backwards again).
> - Actioned Laurent's review comments on docs patch.
>
> Original cover letter:
>
> Hopefully I've cc'ed all those that have bashed this problem around previously,
> or are otherwise linked to DRM bridges.
>
> There have been numerous discussions around how DSI support is currently broken
> as it doesn't support initialising the PHY to LP-11 and potentially the clock
> lane to HS prior to configuring the DSI peripheral. There is no op where the
> interface is initialised but HS video isn't also being sent.
> Currently you have:
> - peripheral pre_enable (host not initialised yet)
> - host pre_enable
> - encoder enable
> - host enable
> - peripheral enable (video already running)
>
> vc4 and exynos currently implement the DSI host as an encoder, and split the
> bridge_chain. This fails if you want to switch to being a bridge and/or use
> atomic calls as the state of all the elements split off are not added by
> drm_atomic_add_encoder_bridges.
A typically chain looks like this:
CRTC => Encoder => Bridge A => Bridge B
We have in DRM bridges established what is the "next" bridge - indicated
with the direction of the arrows in the drawing.
This set of patches introduces the concept of "upstream" bridges.
pre_enable_prev_bridge_first would be easier to understand as it uses
the current terminology.
I get that "upstream" is used in the DSI specification - but we are
dealing with bridges that happens to support DSI and more, and mixing
the two terminologies is not good.
Note: Upstream is also used in a bridge doc section - here it should
most likely be updated too.
The current approach set a flag that magically makes the core do something
else. Have you considered a much more explicit approach?
A few helpers like:
drm_bridge_pre_enable_prev_bridge()
drm_bridge_enable_prev_bridge()
drm_bridge_disable_prev_bridge()
drm_bridge_post_disable_prev_bridge()
And then update the core so the relevant function is only called once
for a bridge.
Then the need for DSI lanes in LP-11 can be archived by a call to
drm_bridge_pre_enable_prev_bridge()
This is more explicit than a flag that triggers some magic behaviour.
It may even see uses we have not realised yet.
It is late here - so maybe the above is not a good idea tomorrow - but
right now I like the simplicity of it.
Other than the above I read that a mipi_dsi_host_init() is planned,
which is also explicit and simple - good.
Have we seen a new revision of some of these?
Chances are high that I have missed it then.
Sam
next prev parent reply other threads:[~2022-07-18 20:52 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-04 15:17 [PATCH V2 0/3] DSI host and peripheral initialisation ordering Dave Stevenson
2022-03-04 15:17 ` [PATCH V2 1/4] drm/bridge: Remove duplication from drm_bridge and drm_atomic_bridge chains Dave Stevenson
2022-06-08 11:00 ` Dmitry Baryshkov
2022-07-18 18:16 ` Sam Ravnborg
2022-03-04 15:17 ` [PATCH V2 2/4] drm/bridge: Introduce pre_enable_upstream_first to alter bridge init order Dave Stevenson
2022-09-14 9:46 ` Jagan Teki
2022-03-04 15:17 ` [PATCH V2 3/4] drm/panel: Add prepare_upstream_first flag to drm_panel Dave Stevenson
2022-06-08 11:02 ` Dmitry Baryshkov
2022-10-06 14:25 ` Jagan Teki
2022-10-07 12:55 ` Dave Stevenson
2022-10-17 2:44 ` Jagan Teki
2022-10-18 17:10 ` Dave Stevenson
2022-03-04 15:17 ` [PATCH V2 4/4] drm/bridge: Document the expected behaviour of DSI host controllers Dave Stevenson
2022-03-18 12:25 ` [PATCH V2 0/3] DSI host and peripheral initialisation ordering Dave Stevenson
2022-04-05 11:43 ` Dave Stevenson
2022-05-11 14:58 ` Marek Szyprowski
2022-05-11 15:47 ` Marek Vasut
2022-05-11 17:29 ` Marek Szyprowski
2022-05-13 14:01 ` Jagan Teki
2022-05-11 15:47 ` Dave Stevenson
2022-05-18 14:05 ` Marek Szyprowski
2022-05-18 22:53 ` Andrzej Hajda
2022-05-19 12:56 ` Dave Stevenson
2022-06-08 10:49 ` Dave Stevenson
2022-06-08 10:57 ` Jagan Teki
2022-06-07 19:46 ` Jagan Teki
2022-05-13 13:57 ` Jagan Teki
2022-06-10 7:52 ` Lucas Stach
2022-07-06 7:09 ` Frieder Schrempf
2022-07-06 7:13 ` Jagan Teki
2022-07-06 10:27 ` Dave Stevenson
2022-07-06 10:43 ` Frieder Schrempf
2022-07-19 14:36 ` Dave Stevenson
2022-07-18 20:52 ` Sam Ravnborg [this message]
2022-07-19 13:45 ` Dave Stevenson
2022-11-13 13:06 ` Dmitry Baryshkov
2022-11-15 14:14 ` Dave Stevenson
2022-11-15 14:21 ` Dmitry Baryshkov
2022-11-15 14:38 ` Dave Stevenson
2022-11-17 13:24 ` Dmitry Baryshkov
2022-11-17 14:34 ` Maxime Ripard
2022-11-17 14:35 ` Dmitry Baryshkov
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