From: Andi Shyti <andi.shyti@linux.intel.com>
To: Andi Shyti <andi.shyti@linux.intel.com>
Cc: Andi Shyti <andi.shyti@kernel.org>,
Mika Kuoppala <mika.kuoppala@linux.intel.com>,
intel-gfx@lists.freedesktop.org,
Stuart Summers <stuart.summers@intel.com>,
dri-devel@lists.freedesktop.org,
Matt Roper <matthew.d.roper@intel.com>
Subject: Re: [PATCH v2 1/2] drm/i915: Sanitycheck MMIO access early in driver load
Date: Tue, 21 Mar 2023 18:15:33 +0100 [thread overview]
Message-ID: <ZBnmNdPMG/Hawmj/@ashyti-mobl2.lan> (raw)
In-Reply-To: <20230321170936.478631-2-andi.shyti@linux.intel.com>
> We occasionally see the PCI device in a non-accessible state at the
> point the driver is loaded. When this happens, all BAR accesses will
> read back as 0xFFFFFFFF. Rather than reading registers and
> misinterpreting their (invalid) values, let's specifically check for
> 0xFFFFFFFF in a register that cannot have that value to see if the
> device is accessible.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Andi
next prev parent reply other threads:[~2023-03-21 17:16 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-21 17:09 [PATCH v2 0/2] Report MMIO communication problems more clearly Andi Shyti
2023-03-21 17:09 ` [PATCH v2 1/2] drm/i915: Sanitycheck MMIO access early in driver load Andi Shyti
2023-03-21 17:15 ` Andi Shyti [this message]
2023-03-21 21:55 ` Matt Roper
2023-03-21 22:43 ` Andi Shyti
2023-03-22 8:40 ` [Intel-gfx] " Andrzej Hajda
2023-03-21 17:09 ` [PATCH v2 2/2] drm/i915: Check for unreliable MMIO during forcewake Andi Shyti
2023-03-21 17:16 ` Andi Shyti
2023-03-22 9:10 ` [Intel-gfx] " Andrzej Hajda
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